M48Z512A M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
- Integrated, ultra low power SRAM, power-fail
control circuit, and battery
- Conventional SRAM operation; unlimited
)WRITE cycles t(s- 10 years of data retention in the absence of cpower du- Automatic power-fail chip deselect and WRITE roprotection P- Two WRITE protect voltages: te(VPFD = power-fail deselect voltage) le M48Z512A: VCC = 4.75 to 5.5 V;
4.5 V ≤ VPFD ≤ 4.75 V
so M48