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CY7C142 Datasheet PDF
- 2K x 8 Dual-Port Static RAM - Data
CY7C132, CY7C136 CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM Features - True dual-ported memory cells that enable simultaneous reads of the same memory location - 2K x 8 organization - 0.65 micron CMOS for optimum speed and power - High speed access: 15 ns - Low operating power: ICC = 110 mA (maximum) - Fully asynchronous operation - Automatic power-down - Master CY7C132, CY7C136, CY7C136A[1] easily expands data bus width to 16 or more bits using slave CY7C142, CY7C146 - BUSY output
Cypress Semiconductor - (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture - RAM
PRELIMINARY CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 250-MH- clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 500 MHz) @ 250 MH- Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two output clocks (C and C) account for clock skew and flight time mismatching Echo c
Cypress Semiconductor
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