Features
80C51 Core
12 or 6 Clocks per Instruction (X1 and X2 Modes) 256 Bytes Scratchpad RAM Dual Data Pointer Two 16-bit Timer, Counters: T0 and T1 T83C5121 with 16 Kbytes Mask ROM T85C5121 with 16 Kbytes Code RAM T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM On-chip Expanded RAM (XRAM): 256 Bytes Versatile Host Serial Interface Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG): Most Standard Speeds up to 230K bits, s at 7.36 MH- Output Enable Input Mul