SHARC+ Dual Core DSP with ARM Cortex-A5
Preliminary Technical Data ADSP-SC582, 583, 584, 587, 589, ADSP-21583, 584, 587
SYSTEM FEATURES
Dual enhanced SHARC+ high performance floating-point cores Up to 450 MH- per SHARC+ core Up to 5 Mbits (640 kB) L1SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word addressed
ARM Cortex-A5 core 450 MHz, 720 DMIPS with Neon, VFPv4-D16, J