Preliminary Technical Data
FEATURES
8-bit analog-to-digital converters 170 MSPS maximum conversion rate Low PLL clock jitter at 170 MSPS Automatic gain matching Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable output drive strength Odd, even field detection External clock input Regenerated Hsync output Programmable output high impedance control Hsyncs per Vsync counter Sync-on-green pulse filter Pb-free