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What is CY62138FV30?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "2-Mbit (256K x 8) Static RAM".


CY62138FV30 Datasheet PDF - Cypress Semiconductor

Part Number CY62138FV30
Description 2-Mbit (256K x 8) Static RAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY62138FV30 MoBL®
2-Mbit (256K x 8) Static RAM
Features
Very High-speed: 45 ns
Temperature ranges
Industrial: –40 °C to 85 °C
Automotive-A: –40 °C to 85 °C
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62138CV25/30/33
Ultra low standby power
Typical standby current: 1 A
Maximum standby current: 5 A
Ultra low active power
Typical active current: 1.6 mA at f = 1 MHz
Easy memory expansion with CE1, CE2, and OE Features
Automatic power down when deselected
complementary metal oxide semiconductor (CMOS) for
Optimum speed and power
Offered in Pb-free 36-Ball VFBGA, 32-Pin TSOP II, 32-Pin
SOIC, 32-Pin TSOP I and 32-Pin STSOP Packages
Logic Block Diagram
Functional Description
The CY62138FV30[1] is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Place the device into standby mode reducing
power consumption when deselected (CE1 HIGH or CE2 LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-08029 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2010
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CY62138FV30 equivalent
CY62138FV30 MoBL®
Thermal Resistance
Parameter[10]
Description
JA Thermal resistance
(Junction to Ambient)
JC Thermal resistance
(Junction to Case)
Test Conditions
Still air, soldered on a 3 x
4.5 inch, two layer
printed circuit board
SOIC
44.53
24.05
VFBGA TSOP II STSOP TSOP I Unit
38.49 44.16 59.72 50.19 C/W
17.66 11.97 15.38 14.59 C/W
Figure 1. AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
R2
VCC
GND
10%
90%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameter
R1
R2
RTH
VTH
2.5 V (2.2 V to 2.7 V)
16667
15385
8000
1.20
3.0 V (2.7 V to 3.6 V)
1103
1554
645
1.75
Unit
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR [12]
tCDR [10]
tR [13]
Description
Conditions
VCC for data retention
Data retention current
Chip deselect to data retention time
VCC = 1.5 V,
CE1 > VCC 0.2 V or CE2 < 0.2
V, VIN > VCC 0.2 V or VIN < 0.2 V
Operation recovery time
Figure 2. Data Retention Waveform [14]
Ind’l/Auto-A
Min Typ[11] Max Unit
1.5 –
–V
– 1 4 A
0–
45 –
– ns
– ns
DATA RETENTION MODE
VCC
VCC(min)
VDR > 1.5V
VCC(min)
tCDR
tR
CE
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 2 5°C
12. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating
13. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
14. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document #: 001-08029 Rev. *I
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Part Details

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Featured Datasheets

Part NumberDescriptionMFRS
CY62138FV30The function is 2-Mbit (256K x 8) Static RAM. Cypress SemiconductorCypress Semiconductor

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