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What is CY62138EV30?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "2 Mbit (256K x 8) MoBL Static RAM".


CY62138EV30 Datasheet PDF - Cypress Semiconductor

Part Number CY62138EV30
Description 2 Mbit (256K x 8) MoBL Static RAM
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY62138EV30 MoBL®
2 Mbit (256K x 8) MoBLStatic RAM
Features
Very high speed: 45 ns
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62138CV30
Ultra low standby power
Typical standby current: 1 A
Maximum standby current: 7 A
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
Complementary metal oxide semiconducor (CMOS) for
optimum speed and power
Offered in Pb-free 36-ball ball grid array (BGA) package
Logic Block Diagram
Functional Description
The CY62138EV30[1] is a high performance CMOS static RAM
organized as 256K words by eight bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. The device can be put into standby mode reducing
power consumption when deselected (CE HIGH).
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
AAAAAAAAAAAA11120345807691
CE
WE
OE
Data in Drivers
256K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Note
1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05577 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 17, 2011
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CY62138EV30 equivalent
CY62138EV30 MoBL®
Capacitance
Parameter[9]
CIN
COUT
Description
Input capacitance
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ.)
Max
10
10
Thermal Resistance
Parameter[9]
JA
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
BGA
72
8.86
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
Figure 1. AC Test Loads and Waveforms
ALL INPUT PULSES
R2
VCC
GND
10%
90%
90%
10%
Rise Time: 1 V/ns
Fall time: 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
2.50 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR [11]
Description
VCC for data retention
Data retention current
tCDR[9]
tR[12]
Chip deselect to data retention time
Operation recovery time
Conditions
VCC = 1V, CE > VCC 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
Min Typ[10]
1–
– 0.8
0–
45 –
Data Retention Waveform
Unit
pF
pF
Unit
C / W
C / W
Unit
V
Max Unit
–V
3 A
– ns
– ns
DATA RETENTION MODE
VCC
VCC (min.)
VDR > 1.5 V
1.5 V
tCDR
tR
CE
Notes
9. Tested initially and after any design or process changes that may affect these parameters.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
11. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
12. Full device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) 100 s.
Document #: 38-05577 Rev. *C
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Part Details

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Featured Datasheets

Part NumberDescriptionMFRS
CY62138EV30The function is 2 Mbit (256K x 8) MoBL Static RAM. Cypress SemiconductorCypress Semiconductor

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