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PDF LP61L1008AS-12 Data sheet ( Hoja de datos )
| Número de pieza | LP61L1008AS-12 | |
| Descripción | 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM | |
| Fabricantes | AMIC Technology | |
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LP61L1008A
Preliminary
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Features
n Single 3.3V ± 10% power supply
n Access times: 8/10/12 ns (max.)
n Current: Operating: 160/155/150mA (max.)
Standby: 5mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL compatible
General Description
The LP61L1008A is a high speed 1,048,576-bit static
random access memory organized as 131,072 words by
8 bits and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configuration
n Center Power/Ground Pin Configuration
n Common I/O using three-state output
n Output enable and one chip enable inputs for easy
application
n Data retention voltage: 2.0V (min.)
n Available in 32-pin SOJ 300 mil package
The chip enable input is provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
A0
A1
A2
A3
CE
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O8
26 I/O7
25 GND
24 VCC
23 I/O6
22 I/O5
21 A12
20 A11
19 A10
18 A9
17 A8
PRELIMINARY (August, 2001, Version 1.0)
1
AMIC Technology, Inc.
1 page  
LP61L1008A
AC Characteristics (continued)
Symbol
Parameter
LP61L1008A-8 LP61L1008A-10 LP61L1008A-12
Min. Max. Min. Max. Min. Max.
Unit
Write Cycle
tWC Write Cycle Time
tCW Chip Enable to End of Write
tAS Address Setup Time of Write
tAW Address Valid to End of Write
tWP Write Pulse Width
tWR Write Recovery Time
tWHZ Write to Output in High Z
tDW Data to Write Time Overlap
tDH Data Hold from Write Time
tOW Output Active from End of Write
8
6
0
6
6
0
0
4
0
3
- 10 - 12 -
- 7 - 10 -
- 0 - 0-
- 7 - 10 -
- 7 - 8-
- 0 - 0-
4 0 5 05
- 5 - 8-
-0-0-
-3-5-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms
Read Cycle 1(1, 2, 4)
Address
DOUT
tRC
tAA
tOH
tOH
PRELIMINARY (August, 2001, Version 1.0)
5
AMIC Technology, Inc.
5 Page 
Package Information
SOJ 32 (300mil BODY) Outline Dimensions
D
32 17
1 16
b1
LP61L1008A
unit: inches/mm
b
F
F
DETAIL "A"
BASE METAL
WITH PLATING
SECTION F-F
DETAIL "A"
HE
ys
b
SEATING PLANE
e
0.004 y
y
e1
Symbol
A
A1
A2
b
b1
c
D
HE
E
e1
e
s
y
Dimensions in inches
Min. Nom. Max.
0128 0.132 0.140
0.052
-
-
0.095 0.100 0.105
0.016 0.018 0.020
0.026 0.028 0.032
0.006 0.008 0.012
0.820 0.825 0.830
0.330 0.335 0.340
0.295 0.300 0.305
0.260 0.267 0.274
- 0.050 -
- - 0.048
- - 0.004
Dimensions in mm
Min. Nom. Max.
3.25 3.35 3.56
2.08 -
-
2.41 2.54 2.67
0.41 0.46 0.51
0.66 0.71 0.81
0.15 0.20 0.30
20.83 20.96 21.08
8.39 8.51 8.63
7.49 7.62 7.75
6.61 6.78 6.96
- 1.27 -
- - 1.22
- - 0.10
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E doesn't include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY (August, 2001, Version 1.0)
11
AMIC Technology, Inc.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LP61L1008AS-12.PDF ] | |
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| LP61L1008AS-12 | 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM | AMIC Technology |
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