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Datasheet 74LS73 Equivalent ( PDF )

N.º Número de pieza Descripción Fabricantes Category
174LS73Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent ne
Fairchild Semiconductor
Fairchild Semiconductor		flip-flop
274LS73Dual J-K Flip-Flops(with Clear)

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20
Hitachi Semiconductor
Hitachi Semiconductor		flip-flop
374LS73DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to
Motorola Semiconductors
Motorola Semiconductors		flip-flop
474LS73ADual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent ne
Fairchild Semiconductor
Fairchild Semiconductor		flip-flop
574LS73ADual J-K Flip-Flops(with Clear)

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20
Hitachi Semiconductor
Hitachi Semiconductor		flip-flop


74L Datasheet ( Hoja de datos ) - resultados coincidentes

N.º Número de pieza Descripción Fabricantes Catagory
174L74Dual Positive Edge Triggered D Flip-Flop

National Semiconductor
National Semiconductor		flip-flop
274LCX00Low Voltage Quad 2-Input NAND Gate

74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs December 2013 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs Features ■ 5V tolerant inputs ■ 2.3V–3.6V VCC specifications provided ■ 5.2ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high i
Fairchild Semiconductor
Fairchild Semiconductor		gate
374LCX00Low voltage CMOS QUAD 2-Input NAND gate

74LCX00 Low-voltage CMOS quad dual input NAND gate with 5 V tolerant inputs Datasheet −production data Features ■ 5 V tolerant inputs ■ High speed – tPD = 4.3 ns (max.) at VCC = 3 V ■ Power-down protection on inputs and outputs ■ Symmetrical output impedance – |IOH| = IOL = 24 mA (m
ST Microelectronics
ST Microelectronics		gate
474LCX00MLow Voltage Quad 2-Input NAND Gate

74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs December 2013 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs Features ■ 5V tolerant inputs ■ 2.3V–3.6V VCC specifications provided ■ 5.2ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high i
Fairchild Semiconductor
Fairchild Semiconductor		gate
574LCX00MTCLow Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs

74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs March 1995 Revised March 1999 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs General Description The LCX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys
Fairchild Semiconductor
Fairchild Semiconductor		gate
674LCX00MTCXLow Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs

74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs March 1995 Revised March 1999 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs General Description The LCX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys
Fairchild Semiconductor
Fairchild Semiconductor		gate
774LCX00SJLow Voltage Quad 2-Input NAND Gate

74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs December 2013 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs Features ■ 5V tolerant inputs ■ 2.3V–3.6V VCC specifications provided ■ 5.2ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high i
Fairchild Semiconductor
Fairchild Semiconductor		gate



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Número de pieza Descripción Fabricantes PDF
SPS122

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