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What is 3256E?

This electronic component, produced by the manufacturer "Lattice Semiconductor", performs the same function as "In-System Programmable High Density PLD".


3256E Datasheet PDF - Lattice Semiconductor

Part Number 3256E
Description In-System Programmable High Density PLD
Manufacturers Lattice Semiconductor 
Logo Lattice Semiconductor Logo 


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ispLSI® 3256E
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 256 I/O Pins
— 12000 PLD Gates
— 512 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 100 MHz Maximum Operating Frequency
tpd = 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
ORP
ORP
H3 H2 H1 H0
ORP
ORP
G3 G2 G1 G0
Boundary
Scan
A0 D Q F3
A1
DQ
OR
F2
A2
Array D Q
F1
DQ
A3
Twin
F0
D Q GLB
DQ
OR
B0
Array D Q
E3
B1 D Q E2
B2 E1
Global Routing Pool
B3 E0
C0 C1 C2 C3
ORP
ORP
D0 D1 D2 D3
ORP
ORP
Description
0139A/3256E
The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connectivity between all of these ele-
ments. The ispLSI 3256E features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256E offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3256E device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256E
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays and eight
outputs which can be configured to be either combinato-
rial or registered. All Twin GLB inputs come from the
GRP.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2002
3256e_08
1

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3256E equivalent
Specifications ispLSI 3256E
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
3ns 10% to 90%
1.5V
1.5V
See Figure 2
Table 2-0003/3256E
Figure 2. Test Load
Device
Output
+ 5V
R1
R2
Test
Point
CL*
Output Load conditions (See Figure 2)
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C at VOH -0.5V
Active Low to Z
at VOL+0.5V
R1
470
470
R2
390
390
390
390
CL
35pF
35pF
35pF
5pF
470
3905pF
Table 2 - 0004A
*CL includes Test Fixture and Probe Capacitance.
0213A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VOL
Output Low Voltage
IOL= 8 mA
– – 0.4 V
VOH
Output High Voltage
IOH = -4 mA
2.4 – – V
IIL Input or I/O Low Leakage Current
0V VIN VIL (Max.)
– – -10 µA
IIH Input or I/O High Leakage Current
3.5V VIN VCC
– – 10 µA
IIL-isp Bscan/ispEN Input Low Leakage Current
0V VIN VIL
– – -150 µA
IIL-PU I/O Active Pull-Up Current
0V VIN VIL
– – -150 µA
IOS1
Output Short Circuit Current
VCC= 5V, VOUT = 0.5V
– – -200 mA
ICC2,4
Operating Power Supply Current
VIL= 0.0V, VIH= 3.0V
fTOGGLE = 1 MHz
– 300 – mA
Table 2 - 0007isp/3256E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using sixteen 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum ICC.
5


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