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What is A3959SLB?

This electronic component, produced by the manufacturer "Allegro MicroSystems", performs the same function as "DMOS FULL-BRIDGE PWM MOTOR DRIVER".


A3959SLB Datasheet PDF - Allegro MicroSystems

Part Number A3959SLB
Description DMOS FULL-BRIDGE PWM MOTOR DRIVER
Manufacturers Allegro MicroSystems 
Logo Allegro MicroSystems Logo 


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3959
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
A3959SLB (SOIC)
CP 1
CP2 2
CP1 3
PHASE
θ
4
ROSC 5
GROUND 6
GROUND 7
LOGIC SUPPLY 8 VDD
ENABLE 99
PFD2 10
BLANK 11
PFD1 12
24 VREG
23 SLEEP
NC 22
NO
CONNECTION
21 OUTB
VBB 20 LOAD SUPPLY
19 GROUND
18 GROUND
17 SENSE
16 OUTA
NC
15
NO
CONNECTION
14 EXT MODE
÷10 13 REF
Dwg. PP-069-4
Note that the A3959SLB(SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.
ABSOLUTE MAXIMUM RATINGS
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3959SB, A3959SLB, and A3959SLP are capable of
output currents to ±3 A and operating voltages to 50 V. Internal fixed
off-time PWM current-control timing circuitry can be adjusted via
control inputs to operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during PWM
operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of supply and charge pump, and
crossover-current protection. Special power-up sequencing is not
required.
The A3959SB/SLB/SLP is a choice of three power packages, a
24-pin plastic DIP with a copper batwing tab (package suffix ‘B’), a
24-lead plastic SOIC with a copper batwing tab (package suffix ‘LB’),
and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal
pad (suffix ‘LP’). In all cases, the power tab is at ground potential and
needs no electrical isolation. Each package is available in a lead-
free version (100% matte tin leadframe).
Load Supply Voltage, VBB ......................... 50 V
Output Current, IOUT (Repetitive) ........... ±3.0 A
(Peak, <3 µs) ................................... ±6.0 A
Logic Supply Voltage, VDD ....................... 7.0 V
Logic Input Voltage Range, VIN
(Continuous) ............ -0.3 V to VDD + 0.3 V
(tw <30 ns) ............... -1.0 V to VDD + 1.0 V
Sense Voltage, VS (Continuous) .............. 0.5 V
(tw <3 µs) ........................................... 2.5 V
Reference Voltage, VREF ............................ VDD
Package Power Dissipation (TA = 25°C), PD
A3959SB ........................................ 3.3 W*
A3959SLB ...................................... 2.5 W*
A3959SLP ...................................... 3.1 W*
Operating Temp. Range, TA .... -20°C to +85°C
Junction Temperature, TJ ..................... +150°C
Storage Temp. Range, TS ..... -55°C to +150°C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
FEATURES
s ±3 A, 50 V Output Rating
s Low rDS(on) Outputs (270 m, Typical)
s Mixed, Fast, and Slow Current-Decay Modes
s Synchronous Rectification for Low Power Dissipation
s Internal UVLO and Thermal-Shutdown Circuitry
s Crossover-Current Protection
s Internal Oscillator for Digital PWM Timing
Always order by complete part number:
Part Number
A3959SB
Package
24-pin batwing DIP
RθJA*
38°C/W
A3959SB-T 24-pin batwing DIP; Lead-free
38°C/W
A3959SLB
24-lead batwing SOIC
50°C/W
A3959SLB-T 24-lead batwing SOIC; Lead-free 50°C/W
A3959SLP
28-lead thin shrink SOIC
40°C/W
A3959SLP-T 28-lead thin shrink SOIC; Lead-free 40°C/W
RθJT
6°C/W
6°C/W
6°C/W
6°C/W
* Double-sided board, one square inch copper each side. See also, Layout, page 7.

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A3959SLB equivalent
3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
VREG. This internally generated voltage is used to operate
the sink-side DMOS outputs. The VREG terminal should
be decoupled with a 0.22 µF capacitor to ground. VREG is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump. The charge pump is used to generate a
gate-supply voltage greater than VBB to drive the source-
side DMOS gates. A 0.22 µF ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22 µF ceramic capacitor should be connected between
CP and VBB to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.
PHASE Logic. The PHASE input terminal determines if
the device is operating in the “forward” or “reverse” state.
PHASE
0
OUTA
Low
OUTB
High
1
High
Low
ENABLE Logic. The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.
ENABLE
0
1
Outputs
Chopped
On
EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high,
slow decay mode, both sink drivers are on with ENABLE
low.
EXT MODE
Decay
0 Fast
1 Slow
Current Regulation. Load current is regulated by an
internal fixed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (RS) and the
applied analog reference voltage (VREF):
ITRIP = VREF/10RS
At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
fixed off-time period. The current path during
recirculation is determined by the configuration of slow/
mixed/fast current-decay mode via PFD1 and PFD2.
Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the ROSC
terminal to VDD. Typical value of 4 MHz is set with a
51 kresistor. The allowable range of the resistor is from
20 kto 100 k.
fOSC = 204 x 109/ROSC.
If ROSC is not pulled up to VDD, it must be shorted to
ground.
Fixed Off Time. The A3959 is set for a fixed off time of
96 cycles of the internal oscillator, typically 24 µs with a
4 MHz oscillator.
www.allegromicro.com
5


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Featured Datasheets

Part NumberDescriptionMFRS
A3959SLBThe function is DMOS FULL-BRIDGE PWM MOTOR DRIVER. Allegro MicroSystemsAllegro MicroSystems
A3959SLB-TThe function is DMOS FULL-BRIDGE PWM MOTOR DRIVER. Allegro MicroSystemsAllegro MicroSystems
A3959SLPThe function is DMOS FULL-BRIDGE PWM MOTOR DRIVER. Allegro MicroSystemsAllegro MicroSystems

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