Datasheet ICSSSTUAF32866C Equivalent ( PDF )

N.º	Número de pieza	Descripción	Fabricantes	PDF
1	ICSSSTUAF32866C	25-BIT CONFIGURABLE REGISTERED BUFFER DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32866C design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing	IDT

ICSSSTUAF328 Datasheet ( Hoja de datos ) - resultados coincidentes

Número de pieza	Descripción	Fabricantes	PDF
ICSSSTUAF32869A	14-BIT CONFIGURABLE REGISTERED BUFFER DATASHEET 14-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32869A The ICSSSTUAF32869A includes a parity checking function. The ICSSSTUAF32869A accepts a parity bit from the memory controller at its input pin PARIN one or two cycles after the correspo	IDT
ICSSSTUAF32868B	28-BIT CONFIGURABLE REGISTERED BUFFER DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32868B QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit	IDT
ICSSSTUAF32868A	28-BIT CONFIGURABLE REGISTERED BUFFER DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL ICSSSTUAF32868A Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, exc	IDT

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