HD74HC279 PDF Datasheet

HD74HC279 Quad. S–R Latches Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low, output is high, but th

DM74LS279 Quad S-R Latch August 1986 Revised March 2000 DM74LS279 Quad S-R Latch General Description The DM74LS279 consists of four individual and independent Set-Reset Latches with active low inputs. Two of the four latches have an additional S input ANDed with the primary S i

54279 DM74279 Quad Set-Reset Latch June 1989 54279 DM74279 Quad Set-Reset Latch General Description This device contains four independent set-reset type flipflops with one Q output each Connection Diagram Dual-In-Line Package TL F 9785 – 1 Order Number 54279DMQB 54279FMQB

HD74HC20 Dual 4-input NAND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA ma

HD74HC21 Dual 4-input AND Gates Features • • • • • High Speed Operation: tpd = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA ma