HD74HC27 PDF Datasheet

HD74HC27 Triple 3-input NOR Gates Features • • • • • High Speed Operation: tpd = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C) Pin Arrangement 1A 1B 2A 2B 2C 2Y GND 1 2 3 4 5 6 7 (Top view) 14 VCC 13 1C 12

HD74HC273 Octal D-type Flip-Flops (with Clear) Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Features • • • • • Hig

HD74HC273 Octal D-type Flip-Flops (with Clear) REJ03D0604-0300 Rev.3.00 Mar 25, 2009 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low st

HD74HC279 Quad. S–R Latches Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established. And when both inputs are low, output is high, but th