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Datasheet 74VHC08 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 10 | 74VHC08 | QUAD 2-INPUT AND GATE 74VHC08
QUAD 2-INPUT AND GATE
s HIGH SPEED: tPD = 4.3 ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA=25°C s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.) s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN)
s BALANCED PROPAGATION D |
 STMicroelectronics |
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| 9 | 74VHC08 | Quad 2-Input AND Gate 74VHC08 — Quad 2-Input AND Gate
December 2007
74VHC08 Quad 2-Input AND Gate
Features
■ High Speed: tPD = 4.3ns (Typ.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs
■ Low power dissipation: ICC = 2µA (Max.) @ TA = 25 |
 Fairchild Semiconductor |
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| 8 | 74VHC08 | Quad 2-input AND gate 74VHC08; 74VHCT08
Quad 2-input AND gate
Rev. 01 — 30 June 2009
Product data sheet
1. General description
The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A.
The 74VHC0 |
 NXP Semiconductors |
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| 7 | 74VHC08-Q100 | Quad 2-input AND gate 74VHC08-Q100; 74VHCT08-Q100
Quad 2-input AND gate
Rev. 1 — 20 December 2013
Product data sheet
1. General description
The 74VHC08-Q100; 74VHCT08-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standa |
NXP Semiconductors |
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