uPD46365182B Datasheet PDF - Renesas
| Part Number | uPD46365182B | |
| Description | 36M-BIT QDR II SRAM 2-WORD BURST OPERATION | |
| Manufacturers | Renesas | |
| Logo |  |
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There is a preview and uPD46365182B download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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μPD46365092B
μPD46365182B
μPD46365362B
Datasheet
36M-BIT QDRTM II SRAM
2-WORD BURST OPERATION
R10DS0089EJ0400
Rev.4.00
Nov 09, 2012
Description
The μPD46365092B is a 4,194,304-word by 9-bit, the μPD46365182B is a 2,097,152-word by 18-bit and the
μPD46365362B is a 1,048,576-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The μPD46365092B, μPD46365182B and μPD46365362B integrate unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and
K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (13 x 15)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR READ and WRITE operation
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz).
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 1 of 35
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μPD46365092B, μPD46365182B, μPD46365362B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46365362B]
1M x 36
12345678
A CQ# VSS/288M NC/72M W# BW2# K# BW1# R#
B Q27 Q18 D18
A BW3# K BW0# A
C D27 Q28 D19 VSS
A
A
A VSS
D D28 D20 Q19 VSS VSS VSS VSS VSS
E Q29
D29
Q20 VDDQ
VSS
VSS
VSS VDDQ
F Q30
Q21
D21 VDDQ
VDD
VSS
VDD
VDDQ
G D30
D22
Q22 VDDQ
VDD
VSS
VDD
VDDQ
H DLL#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J D31
Q31
D23 VDDQ
VDD
VSS
VDD
VDDQ
K Q32
D32
Q23 VDDQ
VDD
VSS
VDD
VDDQ
L Q33
Q24
D24 VDDQ
VSS
VSS
VSS VDDQ
M D33 Q34 D25 VSS VSS VSS VSS VSS
N D34 D26 Q25 VSS
A
A
A VSS
P Q35 D35 Q26
A
A
C
A
A
R TDO TCK
A
A
A C# A
A
9 10
A
D17
VSS/144M
Q17
D16 Q7
Q16 D15
Q15 D6
D14 Q14
Q13 D13
VDDQ
D12
VREF
Q4
Q12 D3
D11 Q11
D10 Q1
Q10 D9
Q9 D0
A TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
A
D0 to D35
Q0 to Q35
R#
W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Read input
: Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A, 3A and 10A are expansion addresses : 3A for 72Mb
: 3A and 10A for 144Mb
: 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0089EJ0400 Rev.4.00
Nov 09, 2012
Page 5 of 35
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for uPD46365182B electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ uPD46365182B.PDF Datasheet ] | |
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