DataSheet39.com

What is uPD46184362B?

This electronic component, produced by the manufacturer "Renesas", performs the same function as "18M-BIT DDR II SRAM 2-WORD BURST OPERATION".


uPD46184362B Datasheet PDF - Renesas

Part Number uPD46184362B
Description 18M-BIT DDR II SRAM 2-WORD BURST OPERATION
Manufacturers Renesas 
Logo Renesas Logo 


There is a preview and uPD46184362B download ( pdf file ) link at the bottom of this page.





Total 30 Pages



Preview 1 page

No Preview Available ! uPD46184362B datasheet, circuit

μPD46184182B
μPD46184362B
Datasheet
18M-BIT DDR II SRAM
2-WORD BURST OPERATION
R10DS0114EJ0200
Rev.2.00
Nov 09, 2012
Description
The μPD46184182B is a 1,048,576-word by 18-bit and the μPD46184362B is a 524,288-word by 36-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD46184182B and μPD46184362B integrate unique synchronous peripheral circuitry and a burst counter. All input
registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
User programmable impedance output (35 to 70 Ω)
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
R10DS0114EJ0200 Rev.2.00
Nov 09, 2012
Page 1 of 34

line_dark_gray
uPD46184362B equivalent
μPD46184182B, μPD46184362B
Pin Description
Symbol
A0
A
DQ0 to
DQxx
LD#
R, W#
BWx#
K, K#
C, C#
Type
Input
Input/Outpu
t
Input
Input
Input
Input
Input
(1/2)
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. All transactions operate on a burst of two words
(one clock period of bus activity). A0 is used as the lowest order address bit permitting a
random starting address within the burst operation on x18 and x36 devices. These inputs
are ignored when device is deselected, i.e., NOP (LD# = HIGH).
Synchronous Data IOs: Input data must meet setup and hold times around the rising
edges of K and K#. Output data is synchronized to the respective C and C# data clocks
or to K and K# if C and C# are tied to HIGH.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions operate
on a burst of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#
must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K# for each of the two rising edges comprising the
WRITE cycle. See Pin Arrangement for signal to data relationships.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge
of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally
180 degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first output data.
The rising edge of C is used as the output reference for second output data. Ideally, C# is
180 degrees out of phase with C. When use of K and K# as the reference instead of C
and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C#
are fixed to HIGH (i.e. toggle of C and C#)
R10DS0114EJ0200 Rev.2.00
Nov 09, 2012
Page 5 of 34


line_dark_gray

Preview 5 Page


Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for uPD46184362B electronic component.


Information Total 30 Pages
Link URL [ Copy URL to Clipboard ]
Download [ uPD46184362B.PDF Datasheet ]

Share Link :

Electronic Components Distributor


An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists.


SparkFun Electronics Allied Electronics DigiKey Electronics Arrow Electronics
Mouser Electronics Adafruit Newark Chip One Stop


Featured Datasheets

Part NumberDescriptionMFRS
uPD46184362BThe function is 18M-BIT DDR II SRAM 2-WORD BURST OPERATION. RenesasRenesas

Semiconductors commonly used in industry:

1N4148   |   BAW56   |   1N5400   |   NE555   |  

LM324   |   BC327   |   IRF840  |   2N3904   |  



Quick jump to:

uPD4     1N4     2N2     2SA     2SC     74H     BC     HCF     IRF     KA    

LA     LM     MC     NE     ST     STK     TDA     TL     UA    



Privacy Policy   |    Contact Us     |    New    |    Search