PDF STMP3770 Data sheet ( Hoja de datos )

Número de pieza	STMP3770
Descripción	Fifth-Generation Audio/Video Decoder
Fabricantes	SigmaTel
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PRODUCT DATA SHEET STMP3770 Media System on Chip Fifth-Generation Audio/Video Decoder Version 1.04 March 14, 2008 STFM1000 Radio Host, Debug Peer-to-Peer UI: Rotary UI: LED/ Switches MMC/SD/SDIO/ CE-ATA/Triflash SPI/MS FM Tuner eePROM Backlight / Beep SPDIF Out NAND Flash LCD / CCIR-656 USB High-Speed OTG USB Full-Speed OTG 32768-Hz or 32000-Hz Crystal 24.0-MHz Crystal STFM1000 FM Radio Microphone OTP DRI 2x UARTs IrDA-VFIR IR2oCtarIynDteecrfoadcere GPIO / Pinctrl 2xSSP Interface I2IC2C IInntteerfrafcaece Pulse Width I2CSPInDItFeTrfXace Media Interface E20M06C EECMCC8 CD LCCoDntrol InIntteerrffaacece Interrupt Control, 6xTimers, 16xDMAs, JTAG, Trace USB PHY (HS/FUSSOBTG) USB 2.0 OTG DeviUceS/BHost Peripheral AMBA AHB DualPXLTLAL, RTC, xAtLaAl RM PLL and CLUKSGBEN 16KB 16KB I$ D$ ARDMS9P26 320 MHz DDAACC Capless Direct-Drive Headphones DAMmAicpC ROM OOn--CChhipip RAAMM 19268KK xx 2342bbiittss DCP: CCrDypCtoo/Hnatsrho/ l CCIonolntoevr-erSrfpsaiacocnee AADDCC Temperature Low- ResDoCluDtCion CAoDnCvexr1t6er BaLtotewry CRheasrogluerti on ADC 3-Channel DDCC-DDCC/ CoLnDveOrter STMP3770 Stereo Line Out 1.2V 1.8V 3.3V UI: Buttons, Touch-Screen Rechargeable Li-ION, NiMH Battery 5V Input (USB or Wall Supply) OFFICIAL PRODUCT DOCUMENTATION 3/14/08 5-37xx-DS2-1.04-031408 Copyright © 2007–2008 SigmaTel, Inc. All rights reserved. SigmaTel, Inc. makes no warranty for the use of its products, assumes no responsibility for any errors which may appear in this document, and makes no commitment to update the information contained herein. SigmaTel reserves the right to change or discontinue this product at any time, without no- tice. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuits based on information in this document. SigmaTel and the SigmaTel logo are trademarks of SigmaTel, Inc. and may be used to identify SigmaTel products only. Windows Media and the Win- dows logo are trademarks or registered trademarks of Microsoft Corporation in the United States and other countries. Other product and company names contained herein may be trademarks of their respective owners. 1 page OFFICIAL PRODUCT DOCUMENTATION 3/14/08 STMP3770 6. DEFAULT FIRST-LEVEL PAGE TABLE (DFLPT) ..................................................................... 125 6.1. Overview ....................................................................................................................................... 125 6.2. Operation ...................................................................................................................................... 125 6.2.1. Memory Map ................................................................................................................... 126 6.2.2. Default First-Level Page Table PIO Register Map Entry 2048 ........................................ 128 7. DIGITAL CONTROL AND ON-CHIP RAM ................................................................................. 129 7.1. Overview ....................................................................................................................................... 129 7.2. SRAM Controls ............................................................................................................................. 130 7.3. Miscellaneous Controls ................................................................................................................. 131 7.3.1. Performance Monitoring .................................................................................................. 131 7.3.2. High-Entropy PRN Seed ................................................................................................. 131 7.3.3. Write-Once Register ........................................................................................................ 131 7.3.4. Microseconds Counter .................................................................................................... 131 7.4. Programmable Registers .............................................................................................................. 131 7.4.1. DIGCTL Control Register Description ............................................................................. 131 7.4.2. DIGCTL Status Register Description .............................................................................. 135 7.4.3. Free-Running HCLK Counter Register Description ......................................................... 137 7.4.4. On-Chip RAM Control Register Description .................................................................... 137 7.4.5. On-Chip RAM Repair Address Register Description ....................................................... 138 7.4.6. On-Chip ROM Control Register Description .................................................................... 138 7.4.7. Software Write-Once Register Description ...................................................................... 139 7.4.8. Entropy Register Description .......................................................................................... 139 7.4.9. Entropy Latched Register Description ............................................................................. 140 7.4.10. SJTAG Debug Register Description .............................................................................. 140 7.4.11. Digital Control Microseconds Counter Register Description ......................................... 142 7.4.12. Digital Control Debug Read Test Register Description ................................................. 142 7.4.13. Digital Control Debug Register Description ................................................................... 143 7.4.14. SRAM BIST Control and Status Register Description ................................................... 143 7.4.15. SRAM Status Register 0 Description ............................................................................ 144 7.4.16. SRAM Status Register 1 Description ............................................................................ 145 7.4.17. SRAM Status Register 2 Description ............................................................................ 145 7.4.18. SRAM Status Register 3 Description ............................................................................ 146 7.4.19. SRAM Status Register 4 Description ............................................................................ 146 7.4.20. SRAM Status Register 5 Description ............................................................................ 147 7.4.21. SRAM Status Register 6 Description ............................................................................ 147 7.4.22. SRAM Status Register 7 Description ............................................................................ 148 7.4.23. SRAM Status Register 8 Description ............................................................................ 148 7.4.24. SRAM Status Register 9 Description ............................................................................ 149 7.4.25. SRAM Status Register 10 Description .......................................................................... 150 7.4.26. SRAM Status Register 11 Description .......................................................................... 150 7.4.27. SRAM Status Register 12 Description .......................................................................... 151 7.4.28. SRAM Status Register 13 Description .......................................................................... 152 7.4.29. Digital Control Scratch Register 0 Description .............................................................. 153 7.4.30. Digital Control Scratch Register 1 Description .............................................................. 153 7.4.31. Digital Control ARM Cache Register Description .......................................................... 153 7.4.32. Debug Trap Range Low Address Description ............................................................... 154 7.4.33. Debug Trap Range High Address Description .............................................................. 155 7.4.34. Digital Control Chip Revision Register Description ....................................................... 155 7.4.35. AHB Statistics Control Register Description .................................................................. 156 7.4.36. AHB Layer 0 Transfer Count Register Description ........................................................ 156 7.4.37. AHB Layer 0 Performance Metric for Stalled Bus Cycles Register Description ............ 157 7.4.38. AHB Layer 0 Performance Metric for Valid Bus Cycles Register Description ............... 158 7.4.39. AHB Layer 1 Transfer Count Register Description ........................................................ 158 7.4.40. AHB Layer 1 Performance Metric for Stalled Bus Cycles Register Description ............ 159 7.4.41. AHB Layer 1 Performance Metric for Valid Bus Cycles Register Description ............... 159 7.4.42. AHB Layer 2 Transfer Count Register Description ........................................................ 160 7.4.43. AHB Layer 2 Performance Metric for Stalled Bus Cycles Register Description ............ 160 7.4.44. AHB Layer 2 Performance Metric for Valid Bus Cycles Register Description ............... 161 7.4.45. AHB Layer 3 Transfer Count Register Description ........................................................ 162 7.4.46. AHB Layer 3 Performance Metric for Stalled Bus Cycles Register Description ............ 162 7.4.47. AHB Layer 3 Performance Metric for Valid Bus Cycles Register Description ............... 163 7.4.48. Default First-Level Page Table Movable PTE Locator 0 Description ............................ 163 7.4.49. Default First-Level Page Table Movable PTE Locator 1 Description ............................ 164 5-37xx-DS2-1.04-031408 Contents 5 5 Page OFFICIAL PRODUCT DOCUMENTATION 3/14/08 STMP3770 15.3.23. DCP Channel 1 Options Register Description ............................................................ 504 15.3.24. DCP Channel 2 Command Pointer Address Register Description .............................. 504 15.3.25. DCP Channel 2 Semaphore Register Description ...................................................... 505 15.3.26. DCP Channel 2 Status Register Description ............................................................... 506 15.3.27. DCP Channel 2 Options Register Description ............................................................ 508 15.3.28. DCP Channel 3 Command Pointer Address Register Description .............................. 508 15.3.29. DCP Channel 3 Semaphore Register Description ...................................................... 509 15.3.30. DCP Channel 3 Status Register Description ............................................................... 510 15.3.31. DCP Channel 3 Options Register Description ............................................................ 512 15.3.32. Color-Space Conversion Control Register 0 Description ............................................ 512 15.3.33. Color-Space Conversion Status Register Description ................................................. 514 15.3.34. Color-Space Conversion Output Buffer Parameters Register Description .................. 515 15.3.35. Color-Space Conversion Input Buffer Parameters Register Description ..................... 515 15.3.36. Color-Space RGB Frame Buffer Pointer Description .................................................. 516 15.3.37. Color-Space Luma (Y) Buffer Pointer Description ....................................................... 517 15.3.38. Color-Space Chroma (U/Cb) Buffer Pointer Description ............................................. 517 15.3.39. Color-Space Chroma (V/Cr) Buffer Pointer Description .............................................. 518 15.3.40. Color-Space Conversion Coefficient Register 0 Description ....................................... 518 15.3.41. Color-Space Conversion Coefficient Register 1 Description ....................................... 519 15.3.42. Color-Space Conversion Coefficient Register 2 Description ....................................... 520 15.3.43. Color-Space Conversion X-Scaling Register Description ........................................... 520 15.3.44. Color-Space Conversion Y-Scaling Register Description ........................................... 521 15.3.45. DCP Debug Select Register Description ..................................................................... 522 15.3.46. DCP Debug Data Register Description ....................................................................... 522 15.3.47. DCP Version Register Description .............................................................................. 523 16. SYNCHRONOUS SERIAL PORTS (SSP) .................................................................................. 525 16.1. Overview ..................................................................................................................................... 525 16.2. External Pins ............................................................................................................................... 526 16.3. Bit Rate Generation .................................................................................................................... 526 16.4. Frame Format for SPI and SSI ................................................................................................... 526 16.5. Motorola SPI Mode ..................................................................................................................... 527 16.5.1. SPI DMA Mode ............................................................................................................. 527 16.5.2. Motorola SPI Frame Format .......................................................................................... 527 16.5.3. Motorola SPI Format with Polarity=0, Phase=0 ............................................................ 527 16.5.4. Motorola SPI Format with Polarity=0, Phase=1 ............................................................ 529 16.5.5. Motorola SPI Format with Polarity=1, Phase=0 ............................................................ 529 16.5.6. Motorola SPI Format with Polarity=1, Phase=1 ............................................................ 531 16.6. Texas Instruments Synchronous Serial Interface (SSI) Mode .................................................... 532 16.7. SD/SDIO/MMC Mode .................................................................................................................. 533 16.7.1. SD/MMC Command/Response Transfer ....................................................................... 533 16.7.2. SD/MMC Data Block Transfer ....................................................................................... 534 16.7.3. SDIO Interrupts ............................................................................................................. 536 16.7.4. SD/MMC Mode Error Handling ..................................................................................... 536 16.7.5. SD/MMC Clock Control ................................................................................................. 538 16.8. CE-ATA Mode ............................................................................................................................. 538 16.9. MS Mode ..................................................................................................................................... 539 16.9.1. MS Mode I/O Pins ......................................................................................................... 539 16.9.2. Basic MS Mode Protocol ............................................................................................... 539 16.9.3. MS Mode High-Level Operation .................................................................................... 540 16.9.4. MS Mode Four-State Bus Protocol ............................................................................... 540 16.9.5. Wait for Card IRQ .......................................................................................................... 540 16.9.6. Checking Card Status ................................................................................................... 541 16.9.7. MS Mode Error Conditions ............................................................................................ 541 16.9.8. MS Mode Details ........................................................................................................... 543 16.10. Behavior During Reset .............................................................................................................. 543 16.11. Programmable Registers .......................................................................................................... 544 16.11.1. SSP Control Register 0 Description ............................................................................ 544 16.11.2. SD/MMC and MS Command Register 0 Description .................................................. 546 16.11.3. SD/MMC Command Register 1 Description ................................................................ 550 16.11.4. SD/MMC and MS Compare Reference Register Description ...................................... 550 16.11.5. SD/MMC and MS Compare Mask Register Description .............................................. 550 16.11.6. SSP Timing Register Description ................................................................................ 551 16.11.7. SSP Control Register 1 Description ............................................................................ 551 5-37xx-DS2-1.04-031408 Contents 11 11 Page

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