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PDF CY7C4245 Data sheet ( Hoja de datos )
| Número de pieza | CY7C4245 | |
| Descripción | 64/256/512/1K/2K/4K x 18 Synchronous FIFOs | |
| Fabricantes | Cypress Semiconductor | |
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CY7C4425/4205/4215
CY7C4225/4235/4245
64/256/512/1K/2K/4K x 18 Synchronous FIFOs
Features
■ High speed, low power, first-in first-out (FIFO) memories
■ 64 x 18 (CY7C4425)
■ 256 x 18 (CY7C4205)
■ 512 x 18 (CY7C4215)
■ 1K x 18 (CY7C4225)
■ 2K x 18 (CY7C4235)
■ 4K x 18 (CY7C4245)
■ High speed 100 MHz operation (10 ns read/write cycle time)
■ Low power (ICC = 45 mA)
■ Fully asynchronous and simultaneous read and write operation
■ Empty, Full, Half Full, and Programmable Almost Empty/Almost
Full status flags
■ TTL compatible
■ Retransmit function
■ Output Enable (OE) pin
■ Independent read and write enable pins
■ Center power and ground for reduced noise
■ Supports free running 50% duty cycle clock inputs
■ Width Expansion Capability
■ Depth Expansion Capability
■ Available in 64 pin 14 x 14 TQFP, 64 pin 10 x 10 TQFP, and
68-pin PLCC
Functional Description
The CY7C42X5 are high speed, low power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All are
18 bits wide and are pin/functionally compatible to IDT722X5.
The CY7C42X5 can be cascaded to increase FIFO depth.
Programmable features include Almost Full/Almost Empty flags.
These FIFOs provide solutions for a wide variety of data
buffering needs, including high speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN). When WEN is asserted, data is written into the FIFO
on the rising edge of the WCLK signal. While WEN is held active,
data is continually written into the FIFO on each cycle. The
output port is controlled in a similar manner by a free-running
read clock (RCLK) and a read enable pin (REN). In addition, the
CY7C42X5 have an output enable pin (OE). The read and write
clocks may be tied together for single-clock operation or the two
clocks may be run independently for asynchronous read/write
applications. Clock frequencies up to 100 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
should be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices should be tied to VCC.
The CY7C42X5 provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see Table 2). The Half Full flag
shares the WXO pin. This flag is valid in the standalone and
width-expansion configurations. In the depth expansion, this pin
provides the expansion out (WXO) information that is used to
signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one clock
cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
VCC/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65m N-Well CMOS technology. Input ESD
protection is greater than 2001V, and latch-up is prevented by
the use of guard rings.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-45652 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 02, 2008
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CY7C4425/4205/4215
CY7C4225/4235/4245
Flag Operation
The CY7C42X5 devices provide five flag pins to indicate the
condition of the FIFO contents. Empty and Full are synchronous.
PAE and PAF are synchronous if VCC/SMODE is tied to VSS.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN. FF is synchronized to WCLK, i.e., it is exclusively
updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW, regardless
of the state of REN. EF is synchronized to RCLK, i.e., it is exclu-
sively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C42X5 features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described in
the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying
that the FIFO is either Almost Full or Almost Empty. See Table 2
for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
Retransmit
The retransmit feature is beneficial when transferring packets of
data. It enables the receipt of data to be acknowledged by the
receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last RS cycle. A HIGH pulse on
RT resets the internal read pointer to the first physical location of
the FIFO. WCLK and RCLK may be free running but must be
disabled during and tRTR after the retransmit pulse. With every
valid read cycle after retransmit, previously accessed data is
read and the read pointer is incremented until it is equal to the
write pointer. Flags are governed by the relative locations of the
read and write pointers and are updated during a retransmit
cycle. Data written to the FIFO after activation of RT are trans-
mitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Table 2. Flag Truth Table
Number of Words in FIFO
CY7C4425 - 64 x 18
CY7C4205 - 256 x 18 CY7C4215 - 512 x 18 FF PAF HF PAE EF
0
1 to n[2]
0
1 to n[2]
0
1 to n[2]
HH H L L
HH H L H
(n + 1) to 32
(n + 1) to 128
(n + 1) to 256
HH H HH
33 to (64 − (m + 1))
(64 − m)[] to 63
129 to (256 − (m + 1))
(256 − m)[] to 255
257 to (512 − (m + 1))
(512 − m)[] to 511
HH L HH
HL L HH
64 256 512
LL L HH
Number of Words in FIFO
CY7C4225 - 1K x 18
CY7C4235 - 2K x 18
CY7C4245 - 4K x 18 FF PAF HF PAE EF
0
1 to n[2]
0
1 to n[2]
0
1 to n[2]
HH H L L
HH H L H
(n + 1) to 512
(n + 1) to 1024
(n + 1) to 2048
HH H HH
513 to (1024 − (m + 1)) 1025 to (2048 − (m + 1)) 2049 to (4096 − (m + 1))
H
H
L
H
H
(1024 − m)[3] to 1023
(2048 − m)[3] to 2047
(4096 − m)[3] to 4095
HL L HH
1024
2048
4096
LL L HH
Note
2. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127).
3. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/CY7C4235/CY7C4245 n = 127).
Document Number: 001-45652 Rev. **
Page 5 of 22
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CY7C4425/4205/4215
CY7C4225/4235/4245
Switching Waveforms (continued)
Figure 7. Read Cycle Timing
RCLK
REN
tENS
EF
tCLKH
tCLK
tCLKL
tENH
tREF
tA
NO OPERATION
tREF
Q0–Q17
OE
WCLK
tOLZ
tOE
tSKEW2 [19]
VALID DATA
tOHZ
WEN
RS
REN, WEN,
LD
EF,PAE
FF,PAF,
HF
Q0–Q17
Figure 8. Reset Timing[20]
tRS
tRSR
tRSF
tRSF
tRSF
[21]
OE = 1
OE = 0
Notes:
19. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
20. The clocks (RCLK, WCLK) can be free-running during reset.
21. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
Document Number: 001-45652 Rev. **
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| PDF Descargar | [ Datasheet CY7C4245.PDF ] | |
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