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PDF ISL9206A Data sheet ( Hoja de datos )
| Número de pieza | ISL9206A | |
| Descripción | FlexiHash | |
| Fabricantes | Intersil | |
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®
Data Sheet
July 30, 2008
ISL9206A
FN6651.1
FlexiHash+™ For Battery Authentication
The ISL9206A is a highly cost-effective fixed-secret hash
engine based on Intersil’s second generation FlexiHash™
technology. The device authentication is achieved through a
challenge-response scheme customized for low-cost
applications, where cloning via eavesdropping without
knowledge of the device’s secret code is not economically
viable. When used for its intended applications, the
ISL9206A offers the same level of effectiveness as other
significantly more expensive high-maintenance hash
algorithm and authentication schemes.
The ISL9206A has a wide operating voltage range, and is
suitable for direct powering from a 1-cell Li-ion/Li-Poly or a
3-cell series NiMH battery pack. The ISL9206A can also be
powered by the XSD bus when the bus pull-up voltage is
3.3V or higher. The device connects directly to the cell
terminals of a battery pack, and includes on-chip voltage
regulation circuit, POR, and a non-crystal based oscillator for
bus timing reference.
Communication with the host is achieved through a single
wire XSD interface (a light-weight subset of Intersil’s ISD bus
interface). The XSD bus is compatible for use with serial ports
offered by all 8250 compatible UART’s or a single GPIO
(General Purpose Input and Output) pin of a microprocessor.
A clone prevention solution utilizing the ISL9206A offers
safety and revenue protection at the lowest cost and power,
and is suitable for protection against after-market
replacement for a wide variety of low-cost applications.
Ordering Information
PART NUMBER PART
TEMP.
PACKAGE PKG.
(Note)
MARKING RANGE (°C) (Pb-free) DWG. #
ISL9206ADHZ-T* 206A
-25 to +85 5 Ld SOT-23 P5.064
ISL9206ADRTZ-T* 06A
-25 to +85 8 Ld 2x3 TDFN L8.2x3A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinouts
ISL9206A
(8 LD 2X3 TDFN)
TOP VIEW
ISL9206A
(5 LD SOT-23)
TOP VIEW
VSS 1
NC 2
NC 3
VDD 4
8 XSD
7 NC
6 NC
5 TIO
VSS 1
NC 2
VDD 3
5 XSD
4 TIO
Features
• Challenge-response based authentication scheme using
32-Bit challenge code and 8-Bit authentication code.
• Fast and flexible authentication process. Multi-pass
authentication can be used to achieve the highest security
level if necessary.
• 16x8 OTP ROM stores up to three sets of 32-Bit
host-selectable secrets with additional programmable
memory for storage of up to 48-Bits of ID code and/or pack
information.
• FlexiHash+™ engine uses two sets of 32-Bit secrets for
authentication code generation.
• Non-unique mapping of the secret key to an 8-Bit
authentication code maximizes hacking difficulty due to
need for exhaustive key search (superior to SHA-1).
• Supports 1-cell Li-ion/Li-Poly and 3-cell series NiMH
battery packs (2.6V ~ 4.8V operation), or powered by the
XSD bus.
• XSD single-wire host bus interface communicates with all
8250-compatible UART’s or a single GPIO. Supports CRC
on read data and transfer bit-rate up to 23kbps.
• True “Zero Power” Sleep mode (automatically entered
after a bus inactivity time-out period)
• 5 Ld SOT-23 or 8 Ld TDFN (2mmx3mm) packages
• -25°C to +85°C operating temperature range
• Pb-free (RoHS compliant)
Applications
• Battery Pack Authentication
• Printer Cartridges
• Add-on Accessories
• Other Non-Monetary Authentication Applications
Related Literature
• Application Note AN1165 “ISL6296 Evaluation Kit”
• Application Note AN1167 “Implementing XSD Host Using
a GPIO”
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2008. All Rights Reserved.
FlexiHash is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
1 page  
ISL9206A
Theory of Operation
The ISL9206A contains all circuitry required to support
battery pack authentication based on a challenge-response
scheme. It provides a 16-Byte One-Time Programmable
Read-Only Memory (OTPROM) space for the storage of up
to 96-Bit of secret for the authentication and other user
information. A 32-Bit hash engine (FlexiHash+™) calculates
the authentication result immediately after receiving a 32-Bit
random challenge code. The communication between the
ISL9206A and the host is implemented through the XSD
single-wire communication bus.
Major functions within the ISL9206A include the following, as
shown in Figure 3.
• Power-on reset (POR) and a 2.5V regulator to power all
internal logic circuits.
• 16x8-Bit (16-Byte) OTP ROM, as shown in Table 8. The
first part (two bytes) contains the device default
configuration (DCFG) information (such as the device
address and the XSD communication speed) and the
default trimming (DTRM) information (such as the internal
oscillator frequency trimming). The second part contains
two groups (12-Byte) of memory that can be
independently locked out for the storage of up to three
sets of secret. The last part provides two additional bytes
of space for general-purpose information.
• Control functions, including master control (MSCR) and
status (STAT) registers (as shown in Table 9), interrupt
generation, and the test-related interface.
• FlexiHash+™ engine that includes the 32-Bit highly
non-linear proprietary hash engine, secret selection
register, challenge code register, and the authentication
result register. Table 10 shows all the registers.
• XSD communication bus Interface. The XSD device
address and the communication speed are configured in
the DCFG address in the OTPROM, as given in Table 8.
• Time Base Reference.
The following explains in detail the operation of the ISL9206A.
Power-On Reset (POR)
The ISL9206A powers up in Sleep mode. It remains in Sleep
mode until a power-on ‘break’ command is received from the
host through the XSD bus. The initial power-on ’break’ can be
of any pulse width as long as it is wider than the XSD input de-
glitch time (20µs). Once the ‘break’ command is received, the
internal regulator is powered up. About 20µs after the falling
edge of the power-on ‘break’, an internal POR circuit releases
the reset to the digital block and a POR sequence is started.
During the POR sequence, the ISL9206A initializes itself by
loading the default device configuration information from pre-
assigned locations within the OTP ROM memory. After
initialization, a ‘break’ command is returned to the host to
indicate that the ISL9206A is ready and waiting for a bus
transaction from the host.
HOST BREAK
DEVICE BREAK
XSD BUS
WAVEFORM
60µs
TYP
1.391
BTD
FIGURE 4A. WHEN THE HOST POWER-ON BREAK IS WIDER
THAN 60µs
HOST BREAK
DEVICE BREAK
XSD BUS
WAVEFORM
FIGURE 4B. WHEN THE HOST POWER-ON IS NARROWER
THAN 60µs
FIGURE 4. POWER-ON BREAK SIGNAL TO WAKE-UP THE
ISL9206A FROM SLEEP MODE
Note that the ISL9206A will initiate the power-on sequence
without waiting for the power-on ‘break’ signal to return to the
high state. If the host sends an initial ‘break’ pulse wider than
60µs, the device-ready ‘break’ returned by the ISL9206A will
likely be merged with the pulse sent by the host and,
therefore, may not be detectable. Figure 4 illustrates the
waveforms during the Power-on Reset. Figure 4A represents
the case when the power-on ‘break’ rising edge occurs after
the device starts sending the ‘break’. Figure 4B represents the
case when the power-on ‘break’ finishes before the device
sends its ‘break’. The device break signal is always 1.391
times of the device bit-time (BT, see XSD Bus Interface
section beginning on page 8). Either case in Figure 4 will
wake-up the device successfully if the device is in the sleep
mode.
It is important to keep in mind that a narrow ‘break’ signal will
be taken as a normal bit signal and cause errors, if the
device is not in the sleep mode. For this reason, the narrow
power-on ‘break’ signal should be used only if the user has
to see the returned ‘break’ signal.
Auto-Sleep
While the ISL9206A is powered up and there is no bus
activity for more than about 1 second, the device will
automatically return to Sleep mode. Sleep mode can be
entered independent of whether the XSD bus is held high or
low. While the ISL9206A is in Sleep mode, it is
recommended that the XSD bus be held low to eliminate
current drain through the XSD-pin internal pull-down current.
Auto-Sleep mode can be disabled by clearing the ASLP bit
in the MSCR register. By default, Auto-Sleep is always
enabled at power-up and after a soft reset. Auto-sleep
5 FN6651.1
July 30, 2008
5 Page 
ISL9206A
TABLE 7. SYMBOLS IN THE BUS TRANSACTION PROTOCOL
SYMBOL
DESCRIPTION
MIN TYP MAX
IFGH
IFGD
TAH
TAD
Host inter-frame gap
Device inter-frame gap
Host turn-around time
Device turn-around time
0 BTH
800ms
1 BTD
1 BTH
800ms
1 BTD
Passive CRC Support
The CRC feature only supports the read transaction in the
ISL9206A. When the OPCODE in the instruction is ‘10’, an
8-Bit CRC is automatically calculated for the data bytes
being transferred out. The CRC result is then appended after
the last data byte is read out.
CRC is generated using the DOW CRC polynomial as
shown in Equation 1:
Polynom = 1 + X4 + X5 + X8
(EQ. 1)
BRbrEeAaKk
TtSSDD
WRWITrEiteINISnTsRtrUuCctTioIOnNFFraRmAeME
The CRC generation algorithm is logically illustrated in
Figure 11. Prior to a new CRC calculation, the LFSR (linear
feedback shift register) is initialized to zero. The read data to
be transmitted out is concurrently shifted into the CRC
calculator. After the actual data is transmitted out, the final
content of the LFSR is the resulting CRC value. This value is
transmitted out after the read data, with LSB being
transmitted out first.
Analog Biasing Components and Clock Generation
The analog section of the ISL9206A mainly includes the
Time Base Generator and the internal regulator for powering
the circuits in the ISL9206A.
TIME BASE GENERATOR
A time base generator is included on-chip to provide timing
reference for serial data encoding and decoding at the XSD
bus interface. This eliminates the need for an external
crystal. The time base oscillator is trimmed during
manufacturing to a nominal frequency of 532.5kHz. It has a
frequency tolerance better than 5% over operating supply
voltage and temperature range.
IIFFGGHH
DDAaTtAa FFRraAmMeE11
IIFFGHH DDAaTtAa FFRraAmMeE 22
FIGURE 10A. MULTI-BYTE WRITE INSTRUCTION
BbRrEeAaKk
TtSSDD
RERAeDaIdNSInTsRtUruCcTtiIoOnNFFrRaAmMeE
TtAADD
DDAaTtAaFFRraAmMEe 11
(O(oUuPtUpuTtFfRroOmMsSlaLvAeV)E)
IFIFGGDD
DDAaTtAa FFRraAmMeE 22
(O(UoPuUtpTuFt RfrOoMm SsLlaAvVeE))
FIGURE 10B. MULTI-BYTE READ INSTRUCTION
BbRrEeAaKk
TtSSDD
RERAeDadINISnTsRtrUuCctTioIOnNFFraRmAeME
TtAADD
DDATaAtaFFRrAaMmEe1
(O(oUuPtUpTutFfRroOmMsSlaLvAeV)E)
TtAAHH
NNEXeTxtINInSsTtRruUcCtioTInON
FRraAmMeE
FIGURE 10C. BACK-TO-BACK TRANSACTION (READ FOLLOWED BY WRITE)
FIGURE 10. XSD BUS TRANSACTION PROTOCOL. THE ‘BREAK’ SIGNAL IS OPTIONAL IF THE DEVICE IS AWAKE
SSESeRerIriAiaaLl
DDOAaTuAtaput
11SsTt
SSTtAagGeE
LLSSB
22NnDd
SSTtAaGgeE
33RrdD
SSTtAagGeE
44TtHh
SSTtAaGgeE
55TtHh
SSTtAaGgEe
66TtHh
SSTtAaGgEe
77TthH
SSTtAagGeE
FIGURE 11. THE CRC CALCULATOR FOR THE PASSIVE CRC SUPPORT
88TtHh
SSTtAaGgeE
MMSB
11 FN6651.1
July 30, 2008
11 Page | ||
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