PDF TW8825 Data sheet ( Hoja de datos )

Número de pieza	TW8825
Descripción	LCD Video Processor
Fabricantes	Intersil
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No Preview Available ! Techwell LCD Video Processor with Built-in Decoder, MCU, OSD, TCON and Analog RGB Input Support TW8825 The TW8825 incorporates many of the features required to create multi-purpose in-car LCD display system in a single package. It integrates a high quality 2D comb NTSC/PAL/SECAM video decoder, triple high speed RGB ADCs, high quality scaler, versatile OSD, and high performance MCU. Its image video processing capability includes arbitrary scaling, panoramic scaling, image mirroring, image adjustment and enhancement, Black and White Stretch, etc. On the input side, it supports a rich combination of CVBS, S-video, component video, analog RGB as well as digital YCbCr/RGB inputs. On the output side, it supports a variety of digital panel types with its built-in timing controller. The integration of additional touch screen controller, LED driver controller, PWM and MCU makes this a versatile solution for many portable applications. Applications In-car display Portable DVD and DVRs players Portable media player Analog Video Decoder NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N combination), PAL (60), SECAM with automatic format detection Three 10-bit ADCs and analog clamping circuit. Fully programmable static gain or automatic gain control for the Y or CVBS channel Programmable white peak control for the Y or CVBS channel Software selectable analog inputs allows composite, S-video, analog YPbPr or RGB High quality adaptive 2D comb filter for both NTSC and PAL inputs PAL delay line for color phase error correction Image enhancement with 2D dynamic peaking and CTI. Digital sub-carrier PLL for accurate color decoding Digital horizontal PLL and Advanced synchronization processing for VCR playback and weak signal performance Programmable hue, brightness, saturation, contrast, sharpness High quality horizontal and vertical filtered down scaling with arbitrary scale down ratio Analog RGB Inputs Triple high speed 10-bit ADCs with clamping and programmable gain amplifier SOG and H/V sync support for YPbPr or RGB input Built-in line locked PLL with sync separator Supports input resolution up to 1080p Digital Inputs Support Supports both BT656 and 601 video formats Supports YCbCr/RGB 24-bit input Supports RGB 565 + BT 656 at the same time Supports input resolution up to 1080p TFT Panel Support Built-in programmable timing controller Supports 3, 4, 6 or 8 bits per pixel up to 16.8 million colors with built-in dithering engine Supports digital panel up to XGA resolution Supports Serial (8-bit) RGB panel Font Based On Screen Display Four window font OSD with bordering / shadow 10KB programmable font RAM and 512 display RAM 1/2/3/4 bits/pixel Supports variable width (12/16), height (2~32) SPI Flash Based On Screen Display Nine bitmap based OSD windows through SPI Supports 4/6/8 bits/pixel Supports RLE decompression for one window Supports overlapping between windows FN7934.0 February 20, 2012 1 1-888-INTERSIL or 1-888-468-3774 \| Copyright Intersil Americas Inc. 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. 1 page TW8825 0x241– CLP Position.......................................................................119 0x242– CLP Width...........................................................................119 0x243– RCK Control HI...................................................................119 0x244– RCK Position LO................................................................119 0x245– RCK Width LO....................................................................120 0x246– ROE Control HI...................................................................120 0x247– ROE Position LO................................................................120 0x248– ROE Width LO....................................................................120 0x249– RSP Control........................................................................120 0x24A– RSP Position Control.........................................................120 0x24B– CPL Position Control .........................................................121 0x24C– CPL Position Control LO...................................................121 0x24D– TCON Control I..................................................................121 0x24E– TCON Control II .................................................................121 0x280 – Image Adjustment Register..............................................122 0x281 – Image Adjustment Register..............................................122 0x282 – Image Adjustment Register..............................................122 0x283 – Image Adjustment Register..............................................122 0x284 – Image Adjustment Register..............................................122 0x285 – Image Adjustment Register..............................................123 0x286 – Image Adjustment Register..............................................123 0x287 – Image Adjustment Register..............................................123 0x288 – Image Adjustment Register..............................................123 0x289 – Image Adjustment Register..............................................123 0x28A – Image Adjustment Register..............................................123 0x28B – Image Adjustment Register..............................................123 0x28C – Image Adjustment Register.............................................124 0x2B0 – Image Adjustment Register..............................................124 0x2B1 – Image Adjustment Register..............................................124 0x2B2 – Image Adjustment Register..............................................124 0x2B6 – Image Adjustment Register..............................................124 0x2B7 – Image Adjustment Register..............................................124 0x2BE – Image Adjustment Register.............................................125 0x2BF – Test Pattern Generator Register .....................................125 0x2E0 – LCDC Gamma Control Register.....................................126 0x2E1 – Gamma Table Address Port Register.............................126 0x2E3 – Gamma Table Data Port Register...................................126 0x2E4 – Dither Option Register......................................................126 Dither Output Selection and Calculations.......................................127 0x2F0 – RGB Level Readout Register ..........................................127 0x2F1 – RGB Level Readout Register ..........................................127 0x2F2 – RGB Level Readout Register ..........................................127 0x2F3 – RGB Level Readout Register ..........................................128 0x2F4 – RGB Level Readout Register ..........................................128 0x2F5 – RGB Level Readout Register ..........................................128 0x2F8 – 8-bit Panel Interface Register...........................................128 0x2F9 – 8-bit Panel Interface Register...........................................128 FOSD ................................................................................................129 0x300 – Font OSD Control Register...............................................129 0x301 – Status Register ..................................................................129 0x302 – Test Register......................................................................129 0x303 – Font OSD Control Register...............................................129 0x304 – Font OSD Control Register...............................................130 0x305 – Font OSD Control Register...............................................130 0x306 – OSD RAM Address Register...........................................130 0x307 – OSD RAM Data Port Hi Register.....................................130 0x308 – OSD RAM Data Port Lo Register....................................130 0x309 – Font RAM Address Register............................................131 0x30A – Font RAM Data Port.........................................................131 0x30B – Multi-Color Font Start Position Register..........................131 0x30C – Font OSD Control Register..............................................131 0x30D – Character Color Look-up table data port High Byte Register.............................................................................................131 0x30E – Character Color Look-up table data port Low Byte Register.............................................................................................131 0x310 – OSD Window1 Control Register......................................131 0x311 – OSD Window1 Control Register......................................132 0x312 – OSD Window1 Control Register......................................132 0x313 – OSD Window1 Control Register......................................132 0x314 – OSD Window1 Control Register......................................132 0x315 – OSD Window1 Control Register......................................132 0x316 – OSD Window1 Control Register.....................................132 5 0x317 – OSD Window1 Control Register......................................133 0x318 – OSD Window1 Control Register......................................133 0x319 – OSD Window1 Control Register......................................133 x31A – OSD Window1 Control Register........................................133 0x31B – OSD Window1 Control Register .....................................133 0x31C – OSD Window1 Control Register.....................................134 0x31D – OSD Window1 Control Register ....................................134 0x31E – OSD Window1 Control Register .....................................134 0x31F – OSD Window1 Control Register......................................134 0x320 – OSD Window2 Control Register......................................134 0x321 – OSD Window2 Control Register......................................134 0x322 – OSD Window2 Control Register......................................135 0x323 – OSD Window2 Control Register......................................135 0x324 – OSD Window2 Control Register......................................135 0x325 – OSD Window2 Control Register......................................135 0x326 – OSD Window2 Control Register......................................135 0x327 – OSD Window2 Control Register......................................135 0x328 – OSD Window2 Control Register......................................136 0x329 – OSD Window2 Control Register......................................136 0x32A – OSD Window2 Control Register .....................................136 0x32B – OSD Window2 Control Register .....................................136 0x32C – OSD Window2 Control Register.....................................136 0x32D – OSD Window2 Control Register.....................................137 0x32E – OSD Window2 Control Register .....................................137 0x32F – OSD Window2 Control Register......................................137 0x330 – OSD Window3 Control Register......................................137 0x331 – OSD Window3 Control Register......................................137 0x332 – OSD Window3 Control Register......................................137 0x333 – OSD Window3 Control Register......................................138 0x334 – OSD Window3 Control Register......................................138 0x335 – OSD Window3 Control Register......................................138 0x336 – OSD Window3 Control Register......................................138 0x337 – OSD Window3 Control Register......................................138 0x338 – OSD Window3 Control Register......................................138 0x339 – OSD Window3 Control Register......................................139 0x33A – OSD Window3 Control Register .....................................139 0x33B – OSD Window3 Control Register .....................................139 0x33C – OSD Window3 Control Register.....................................139 0x33D – OSD Window3 Control Register.....................................139 0x33E – OSD Window3 Control Register .....................................139 0x33F – OSD Window3 Control Register......................................140 0x340 – OSD Window4 Control Register......................................140 0x341 – OSD Window4 Control Register......................................140 0x342 – OSD Window4 Control Register......................................140 0x343 – OSD Window4 Control Register......................................140 0x344 – OSD Window4 Control Register......................................140 0x345 – OSD Window4 Control Register......................................141 0x346 – OSD Window4 Control Register......................................141 0x347 – OSD Window4 Control Register......................................141 0x348 – OSD Window4 Control Register......................................141 0x349 – OSD Window4 Control Register......................................141 0x34A – OSD Window4 Control Register .....................................141 0x34B – OSD Window4 Control Register .....................................142 0x34C – OSD Window4 Control Register.....................................142 0x34D – OSD Window4 Control Register.....................................142 0x34E – OSD Window4 Control Register .....................................142 0x34F – OSD Window4 Control Register......................................142 0x350 – Font OSD Control Register..............................................142 0x351 – Font OSD Control Register..............................................143 0x352 – Font OSD Control Register..............................................143 0x353 – Multi-Color Font Start Position Register...........................143 0x354 – Multi-Color Font Start Position Register...........................143 SPI OSD ...........................................................................................143 0x400 – SPIOSD Control Register.................................................143 0x404 ~ 0x406 – SPIOSD RLC Register ......................................144 0x404 – SPIOSD RLC Control.......................................................144 0x405 – SPIOSD RLC Configuration.............................................144 0x406 – SPIOSD RLC Window Select..........................................144 0x40E ~ 0x40F – SPIOSD TIME Adjust Register.........................144 0x40E High Byte...............................................................................144 0x40F High Byte...............................................................................144 0x410 – 8-Bit SPIOSD Look Up Table Access Control Register 145 5 Page Functional Description TW8825 Overview Intersil\|Techwell’s TW8825 LCD Video processor is a highly integrated TFT panel controller. It integrates a high quality 2D comb NTSC/PAL/SECAM video decoder, scalers, timing controller, flexible font based, SPI based OSD engine and high performance MCU. This unique level of mixed signal integration turns a TFT panel into a flexible display system. It incorporates easy-to-operate features in a single package for multi-purpose in-car LCD display, portable DVD and DVRs media players. It contains all the logic required to convert analog or digital video signals in various formats to the signal formats that is necessary to drive various kind of TFT panel types. It supports different panel resolutions depending on the scaler and panel clock settings. It has built-in TCON for direct connecting with low cost TCON-less panel. The integrated analog front-end contains ADCs with clamping circuits and Automatic Gain Control (AGC) circuit as well as anti-aliasing filter to minimize external component count. The built-in video decoder employs proprietary 2D Comb filter Y/C separation technologies to produce exceptionally high quality pictures. The chip's internal logic synchronizes the panel frame rate to the incoming input frame rate. A high quality image-scaling engine is used to convert the different input resolution formats to the output panel resolution. An internal de-interlacing engine also allows interlaced video to be displayed. On Screen Display is supported through on-chip multi-window OSD engine for maximum flexibility. It also has built-in back light controller and panel bias voltage generator to further simplify the system design. The host control interface supports the standard 2-wire serial bus Analog Front-end The analog front-end converts analog video signals to the required digital format. Each channel contains automatic clamping circuit, AGC circuit, anti-aliasing filter and high performance ADCs to minimize the external component used. The clamping circuit restores the signal DC level so it can be properly digitized. The analog inputs source selections are software programmable. Different input source has different signal conditioning logics to properly convert the signal into correct format for further processing Video Decoder SYNC PROCESSOR The decoder sync processor of video input detects horizontal synchronization and vertical synchronization signals in the composite video or in the Y signal of an S-Video signal. The processor contains a digital phase-locked-loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from VCR fast forward or backward. Horizontal Sync Processing The horizontal synchronization processing contains a sync separator, a phase-locked-loop (PLL), and the related decision logic. The horizontal PLL locks onto the extracted horizontal sync in all conditions to provide jitter free image output. From there, the PLL also provides orthogonal sampling raster for the down stream processor. It has wide lock-in range for tracking any non-standard video signal. Vertical Sync Processing The vertical sync separator detects the vertical synchronization pattern in the input video signals. A detection window controls the determination of sync. This provides more reliable synchronization. It simulates the functionality of a PLL without the complexity of a PLL. The field status is determined at vertical synchronization time based on the vertical and horizontal sync relationship. 11 11 Page

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