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PDF ASM2I99448 Data sheet ( Hoja de datos )
| Número de pieza | ASM2I99448 | |
| Descripción | 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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May 2005
ASM2I99448
rev 0.3
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Features
12 LVCMOS compatible clock outputs
Selectable LVCMOS and differential LVPECL
compatible clock inputs
Maximum clock frequency of 350MHz
Maximum clock skew of 150pS
Synchronous output stop in logic low state
eliminates output runt pulses
High–impedance output control
3.3V or 2.5V power supply
Drives up to 24 series terminated clock lines
Ambient temperature range –40°C to +85°C
32–Lead LQFP & TQFP packaging
Supports clock distribution in networking,
telecommunication and computing applications
Pin and Function compatible to MPC9448 and
MPC948
Functional Description
The ASM2I99448 is a 3.3V or 2.5V compatible, 1:12 clock
fanout buffer targeted for high performance clock tree
applications. With output frequencies up to 350 MHz and
output skews less than 150 pS, the device meets the needs
of most demanding clock applications.
The ASM2I99448 is specifically designed to distribute
LVCMOS compatible clock signals up to a frequency of
350MHz. Each output provides a precise copy of the input
signal with a near zero skew. The outputs buffers support
driving of 50Ω terminated transmission lines on the incident
edge: each output is capable of driving either one parallel
terminated or two series terminated transmission lines.
Two selectable, independent clock inputs are available,
providing support of LVCMOS and differential LVPECL
clock distribution systems. The ASM2I99448 CLK_STOP
control is synchronous to the falling edge of the input clock.
It allows the start and stop of the output clock signal only in
a logic low state, thus eliminating potential output runt
pulses. Applying the OE control will force the outputs into
high–impedance mode.
All inputs have an internal pull–up or pull–down resistor
preventing unused and open inputs from floating. The
device supports a 2.5V or 3.3V power supply and an
ambient temperature range of –40°C to +85°C. The
ASM2I99448 is pin and function compatible but
performance–enhanced to the MPC948.
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
May 2005
ASM2I99448
rev 0.3
Table 6. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40°C to +85°C)1
Symbol
fref
fMAX
VPP
VCMR2
tP, REF
tr, tf
tPLH/HL
tPLH/HL
tPLZ, HZ
tPZL, LZ
Characteristics
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
PCLK
PCLK
PCLK to any Q
CCLK to any Q
Min
0
0
400
1.3
1.4
1.6
1.3
Typ
Max
350
350
1000
VCC-0.8
1.03
3.6
3.3
11
11
Unit
MHz
MHz
mV
V
nS
nS
nS
nS
nS
nS
Condition
LVPECL
LVPECL
0.8 to 2.0V
tS Setup time
CCLK to CLK_STOP
PCLK to CLK_STOP
0.0
0.0
nS
nS
tH
tsk(O)
tsk(PP)
tSK(P)
Hold time
Output-to-output Skew
Device-to-device Skew
Output pulse skew4
CCLK to CLK_STOP
PCLK to CLK_STOP
1.0
1.5
PCLK or CCLK to any Q
Using CCLK
Using PCLK
nS
nS
150 pS
2.0 nS
300 pS
400 pS
DCQ Output Duty Cycle
fQ<170 MHz 45
50
55
% DCREF = 50%
tr, tf Output Rise/Fall Time
0.1 1.0 nS 0.55 to 2.4V
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT.
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input
swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP).
3. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse
width, output duty cycle and maximum frequency specifications.
4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 7. DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to +85°C)
Symbol
Characteristics
Min
Typ
Max Unit
Condition
VIH Input high voltage
1.7 VCC + 0.3 V LVCMOS
VIL Input low voltage
-0.3 0.7 V LVCMOS
VPP
VCMR1
Peak-to-peak input voltage
Common Mode Range
PCLK
PCLK
250
1.0
VCC-0.7
mV LVPECL
V LVPECL
IIN Input current2
VOH Output High Voltage
VOL Output Low Voltage
300
µA
VIN=GND or
VIN=VCC
1.8 V IOH= -15 mA3
0.6 V IOL= 15 mA3
ZOUT
ICCQ4
Output impedance
Maximum Quiescent Supply Current
19 Ω
2.0 mA All VCC Pins
Note: 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the VPP (DC) specification.
2. Input pull-up / pull-down resistors influence input current.
3. The ASM2I99448 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines at VCC=2.5V.
4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
5 of 15
5 Page 
May 2005
ASM2I99448
rev 0.3
PCLK
PCLK
VPP
VCMR
CCLK
VCC
VCC ÷2
GND
QX tP(LH) tP(HL)
VCC
VCC ÷2
GND
Figure 11. Propagation Delay (tPD) Test Reference
QX
tP(LH)
tP(HL)
VCC
VCC ÷2
GND
Figure 12. Propagation Delay (tPD) Test Reference
VCC
VCC ÷2
GND
tSK(LH)
tSK(HL)
VCC
VCC ÷2
GND
The pin-to-pin skew is defined as the worst case
difference in propagation between any similar delay path
within a single device
Figure 13. Output–to–Output Skew tSK(LH, HL)
CCLK
VCC
VCC ÷2
GND
QX
tP(LH)
tP(HL)
VCC
VCC ÷2
GND
tSK(P) =| tPHL - tPHL |
Figure 14. Output Pulse Skew (tSK(P) Test Reference
VCC
VCC ÷2
GND
tP
T0
DC (tP ÷T0 Χ 100%)
The time from the output controlled edge to the
non-controlled edge, divided by the time output
controlled edge, expressed as a percentage.
Figure 15. Output Duty Cycle (DC)
TJIT(CC) = |TN -TN + 1|
TN TN + 1
The variation in cycle time of a single between adjacent
cycles, over a random sample of adjacent cycle pairs
Figure 17. Cycle–to–Cycle Jitter Reference
VCC = 3.3V VCC = 2.5V
2.4 1.8V
0.5 0.6V
tF tR
Figure 16. Output Transition Time Test Reference
CCLK
PCLK
CLK_STOP
tS tH
VCC
VCC ÷2
GND
VCC
VCC ÷2
GND
Figure 18. Setup and Hold Time (tS, tH) Test
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ASM2I99448.PDF ] | |
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