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PDF GD25LQ40 Data sheet ( Hoja de datos )
| Número de pieza | GD25LQ40 | |
| Descripción | 1.8V Uniform Sector Dual and Quad Serial Flash | |
| Fabricantes | ELM | |
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http://www.elm-tech.com
GD25LQ40
DATASHEET
1 page  
GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
2. GENERAL DESCRIPTION
http://www.elm-tech.com
The GD25LQ40 (4M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI and QPI mode: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and
I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data
is transferred with speed of 480Mbits/s.
Connection Diagram
8-LEAD SOP
Pin Description
Pin Name
CS#
SO (IO1)
WP# (IO2)
VSS
SI (IO0)
SCLK
HOLD# (IO3)
VCC
I/O
I
I/O
I/O
I/O
I
I/O
8-LEAD USON/WSON
Description
Chip Select Input
Data Output (Data Input Output 1)
Write Protect Input (Data Input Output 2)
Ground
Data Input (Data Input Output 0)
Serial Clock Input
Hold Input (Data Input Output 3)
Power Supply
Block Diagram
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
59 - 5
Rev.1.0
5 Page 
GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1,
the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI
operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
LB3, LB2, LB1 bits.
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that
provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0,
the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register
instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become
read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-
BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection
table for details. The default setting is CMP=0.
SUS1, SUS2 bits.
The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1, and the Program Suspend
will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command
as well as a power-down, power-up cycle.
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit
on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in
to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last
bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or
Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-
out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary,
otherwise the command is rejected, and is not executed. That is CS# must driven high when the number of clock
pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte
is not a full byte, nothing will happen and WEL will not be reset.
59 - 11
Rev.1.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GD25LQ40.PDF ] | |
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