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PDF 74ACT244 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT244 | |
| Descripción | Octal Buffer/Line Driver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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January 2008
74AC244, 74ACT244
Octal Buffer/Line Driver with 3-STATE Outputs
Features
■ ICC and IOZ reduced by 50%
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24mA
■ ACT244 has TTL-compatible inputs
General Description
The AC/ACT244 is an octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus-oriented transmitter/receiver which
provides improved PC board density.
Ordering Information
Order Number
Package
Number
Package Description
74AC244SC
74AC244SJ
74AC244MTC
74AC244PC
74ACT244SC
M20B
M20D
MTC20
N20A
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT244SJ
74ACT244MSA
74ACT244MTC
74ACT244PC
M20D
MSA20
MTC20
N20A
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC244, 74ACT244 Rev. 1.4.0
www.fairchildsemi.com
1 page  
DC Electrical Characteristics for ACT
Symbol Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VOL Maximum LOW Level
Output Voltage
IIN
IOZ
ICCT
IOLD
IOHD
ICC
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum ICC/Input
Minimum Dynamic
Output Current(5)
Maximum Quiescent
Supply Current
VCC (V)
4.5
5.5
Conditions
VOUT = 0.1V or
VCC − 0.1V
4.5 VOUT = 0.1V or
5.5 VCC − 0.1V
4.5 IOUT = −50µA
5.5
4.5 VIN = VIL or VIH,
IOH = 24mA
5.5 VIN = VIL or VIH,
IOH = 24mA(4)
4.5 IOUT = 50µA
5.5
4.5 VIN = VIL or VIH,
IOL = 24mA
5.5 VIN = VIL or VIH,
IOL = 24mA(4)
5.5 VI = VCC, GND
TA = +25°C
Typ.
1.5 2.0
1.5 2.0
1.5 0.8
1.5 0.8
4.49 4.4
5.49 5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±0.1
5.5 VI = VIL, VIH;
VO = VCC, GND
±0.25
5.5 VI = VCC − 2.1V
0.6
5.5 VOLD = 1.65V Max.
5.5 VOHD = 3.85V Min.
5.5 VIN = VCC or GND
4.0
TA = −55°C TA =−40°C
to +125°C to +85°C
Guaranteed Limits
2.0 2.0
2.0 2.0
0.8 0.8
0.8 0.8
4.4 4.4
5.4 5.4
3.70
3.76
4.70
4.76
0.1
0.1
0.50
0.1
0.1
0.44
0.50
0.44
±1.0
±5.0
1.6
50
−50
80.0
±1.0
±2.5
1.5
75
−75
40.0
Units
V
V
V
V
µA
µA
mA
mA
mA
µA
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC244, 74ACT244 Rev. 1.4.0
5
www.fairchildsemi.com
5 Page 
Physical Dimensions (Continued)
Figure 5. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1988 Fairchild Semiconductor Corporation
74AC244, 74ACT244 Rev. 1.4.0
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 74ACT244.PDF ] | |
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