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PDF 74HCT4020-Q100 Data sheet ( Hoja de datos )

Número de pieza 74HCT4020-Q100
Descripción 14-stage binary ripple counter
Fabricantes NXP Semiconductors 
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74HC4020-Q100;
74HCT4020-Q100
14-stage binary ripple counter
Rev. 1 — 23 May 2013
Product data sheet
1. General description
The 74HC4020-Q100; 74HCT4020-Q100 are 14-stage binary ripple counters with a clock
input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel
outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of
CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of
the state of CP. Each counter stage is a static toggle flip-flop.. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC4020-Q100: CMOS level
For 74HCT4020-Q100: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters

1 page




74HCT4020-Q100 pdf
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VI < 0.5 V or VI > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
Tamb = 40 C to +125 C
0.5
-
-
-
-
-
65
[1] -
+7
20
20
25
50
50
+150
500
V
mA
mA
mA
mA
mA
C
mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC
VI
VO
t/V
Tamb
supply voltage
input voltage
output voltage
input transition rise and
fall rate
ambient temperature
except for
Schmitt trigger inputs
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
74HC4020-Q100
Min Typ Max
2.0 5.0 6.0
0 - VCC
0 - VCC
74HCT4020-Q100
Min Typ Max
4.5 5.0 5.5
0 - VCC
0 - VCC
Unit
V
V
V
- - 625 - - - ns/V
- 1.67 139 - 1.67 139 ns/V
- - 83 - - - ns/V
40 +25 +125 40 +25 +125 C
74HC_HCT4020_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 May 2013
© NXP B.V. 2013. All rights reserved.
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74HCT4020-Q100 arduino
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
VI 90 %
negative
pulse
GND
VI
positive
pulse
10 %
GND
VM
10 %
tf
tr
90 %
VM
VI
G
RT
tW
tW
VCC
DUT
VM
tr
tf
VM
VO
CL
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 10. Test circuit for measuring switching times
Table 9. Test data
Type
Input
74HC4020-Q100
74HCT4020-Q100
VI
VCC
3V
tr, tf
6 ns
6 ns
Load
CL
15 pF, 50 pF
15 pF, 50 pF
74HC_HCT4020_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 May 2013
© NXP B.V. 2013. All rights reserved.
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