TH58BVG3S0HBAI4 Datasheet PDF - Toshiba
Part Number | TH58BVG3S0HBAI4 | |
Description | 8 GBIT (1G x 8 BIT) CMOS NAND E2PROM | |
Manufacturers | Toshiba | |
Logo | ||
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TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
8 GBIT (1G × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TH58BVG3S0HBAI4 is a single 3.3V 8 Gbit (8,858,370,048 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 128) bytes × 64 pages × 4096blocks.
The device has a 4224-byte static register which allows program and read data to be transferred between the
register and the memory cell array in 4224-bytes increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 8 Kbytes: 4224 bytes × 64 pages).
The TH58BVG3S0HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TH58BVG3S0HBAI4 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
• Organization
Memory cell array
Register
Page size
Block size
x8
4224 × 128K × 8 × 2
4224 × 8
4224 bytes
(256K + 8K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 4016 blocks
Max 4096 blocks
• Power supply
VCC = 2.7V to 3.6V
• Access time
Cell array to register 55 μs typ. (Single Page Read) / 90μs typ. (Multi Page Read)
Serial Read Cycle
25 ns min (CL=50pF)
• Program/Erase time
Auto Page Program
Auto Block Erase
340 μs/page typ.
2.5 ms/block typ.
• Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
100 μA max
• Package
P-TFBGA63-0911-0.80CZ (Weight: 0.165 g typ.)
• 8bit ECC for each 528Byte is implemented on the chip.
1 2013-09-20C
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TH58BVG3S0HBAI4
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = -40 to 85℃, VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
tCLS
CLE Setup Time
tCLH
CLE Hold Time
tCS CE Setup Time
tCH CE Hold Time
tWP Write Pulse Width
tALS
ALE Setup Time
tALH
ALE Hold Time
tDS Data Setup Time
tDH Data Hold Time
tWC Write Cycle Time
tWH WE High Hold Time
tWW
WP High to WE Low
tRR Ready to RE Falling Edge
tRW Ready to WE Falling Edge
tRP Read Pulse Width
tRC Read Cycle Time
tREA
RE Access Time
tCEA
CE Access Time
tCLR
CLE Low to RE Low
tAR ALE Low to RE Low
tRHOH
RE High to Output Hold Time
tRLOH
RE Low to Output Hold Time
tRHZ
RE High to Output High Impedance
tCHZ
CE High to Output High Impedance
tCSD
CE High to ALE or CLE Don’t Care
tREH
RE High Hold Time
tIR Output-High-impedance-to- RE Falling Edge
tRHW
RE High to WE Low
tWHC
WE High to CE Low
tWHR
WE High to RE Low
tWB WE High to Busy
tRST
Device Reset Time (Ready/Read/Program/Erase)
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
MIN MAX UNIT
12 ⎯
5⎯
20 ⎯
5⎯
12 ⎯
12 ⎯
5⎯
12 ⎯
5⎯
25 ⎯
10 ⎯
100 ⎯
20 ⎯
20 ⎯
12 ⎯
25 ⎯
⎯ 20
⎯ 25
10 ⎯
10 ⎯
25 ⎯
5⎯
⎯ 60
⎯ 20
0⎯
10 ⎯
0⎯
30 ⎯
30 ⎯
60 ⎯
⎯ 100
⎯ 5/5/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
5 2013-09-20C
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for TH58BVG3S0HBAI4 electronic component. |
Information | Total 30 Pages | |
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