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PDF Si5340 Data sheet ( Hoja de datos )
| Número de pieza | Si5340 | |
| Descripción | CLOCK GENERATOR | |
| Fabricantes | Silicon Laboratories | |
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Si5341/40
L OW- J ITTER, 1 0 - O UTPUT, A NY- F REQUENCY, A NY- O UTPUT
CLOCK GENERATOR
Features
Generates up to 10 independent
DCO mode with frequency steps as
output clocks
low as 0.001 ppb
Ultra-low jitter: <100 fs RMS typical Independent output clock supply pins:
MultiSynth™ technology enables any- 3.3 V, 2.5 V, or 1.8 V
frequency synthesis on any-output Built-in power supply filtering and
Highly configurable outputs
regulation
compatible with LVDS, LVPECL, CML, Status monitoring: LOS, LOL
LVCMOS, HCSL, or programmable Serial Interface: I2C or SPI (3-wire or
voltage
4-wire)
Input frequency range:
User programmable (2x) non-volatile
External crystal: 25, 48-54 MHz
OTP memory
Differential clock: 10 to 750 MHz
LVCMOS clock: 10 to 250 MHz
Output frequency range:
Differential: 100 Hz to 712.5 MHz
LVCMOS: 100 Hz to 250 MHz
Output-output skew: 20 ps typ
Adjustable output-output delay
Optional zero delay mode
Independent glitchless on-the-fly
output frequency changes
ClockBuilderTM Pro software utility
simplifies device configuration and
assigns customer part numbers
Si5341: 4 input, 10 output, compact
9x9 mm, 64 QFN
Si5340: 4 input, 4 output, compact
7x7 mm, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Device Selector Guide
Grade
Si534xA
Si534xB
Si534xC
Si534xD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Mode
Integer + Fractional
Integer Only
Applications
9x9 mm
7x7 mm
Ordering Information
See Section 8.
Functional Block Diagram
Si5341/40
IN_SEL[1:0]
IN0 ÷INT
IN1 ÷INT
IN2 ÷INT
XA
XB
FB_IN
OSC
÷INT
PLL
Clock tree generation replacing XOs,
buffers, signal format translators
Any-frequency clock translation
Clocking for FPGAs, processors,
memory
Ethernet switches/routers
OTN framers/mappers/processors
Test equipment & instrumentation
Broadcast video
Description
The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL
with proprietary MultiSynth fractional synthesizer technology to offer a versatile and
high performance clock generator platform. This highly flexible architecture is capable
of synthesizing a wide range of integer and non-integer related frequencies up to
712.5 MHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter
performance with 0 ppm error. Each of the clock outputs can be assigned its own
format and output voltage enabling the Si5341/40 to replace multiple clock ICs and
oscillators with a single device making it a true “clock tree on a chip”.
The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software.
Custom part numbers are automatically assigned using a ClockBuilder Pro for fast,
free, and easy factory pre-programming, or the Si5341/40 can be programmed in-
circuit via I2C and SPI serial interfaces.
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
NVM
I2C/SPI
Control/
Status
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si5341/40
1 page  
Si5341/40
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%,TA = –40 to 85 °C)
Parameter
Ambient Temperature
Junction Temperature
Core Supply Voltage
Output Driver Supply Voltage
Symbol
TA
TJMAX
VDD
VDDA
VDDO
Min
–40
—
1.71
3.14
3.14
2.38
Typ
25
—
1.80
3.30
3.30
2.50
Max Units
85 °C
125 °C
1.89 V
3.47 V
3.47 V
2.62 V
1.71 1.80 1.89
V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Rev. 1.0
5
5 Page 
Si5341/40
Table 5. Differential Clock Output Specifications (Continued)
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Output-Output Crosstalk
Symbol
XTALK
Test Condition
Si5341
Note 4
Si5341
Note 6
Si5340
Note 7
Min Typ Max
— –75 —
— –85 —
— –85 —
Units
dBc
dBc
dBc
Notes:
1. The typical normal mode (or low power mode) LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644
maximum. For normal and low-power modes, the amplitudes are programmable through register settings and can be
stored in NVM. Each output driver can be programmed independently. See Appendix A of the Si5341/40 Reference
Manual.
2. Driver output impedance depends on selected output mode (Normal, Low Power).
3. Measured for 156.25 MHz carrier frequency. Sinewave noise added to VDDO (1.8 V = 50 mVpp, 2.5 V/
3.3 V = 100 mVpp) and noise spur amplitude measured.
OUTx
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
4. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor
at 156.25 MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet
Infrastructure Systems”, guidance on crosstalk minimization.
5. For other amplitudes see Appendix A of the Si5341/40 Reference Manual.
6. See Note 4, but in this case the measurement is across two output clocks that have a single clock between them.
7. Same as Note 4, but the Si5340 has less crosstalk due to the spacing of adjacent outputs.
Table 6. Output Status Pin Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Units
Si5341 Status Output Pins (LOL, INTR), SDA/SDIO2, SDO
Output Voltage
VOH
IOH = –2 mA VDDIO1 x 0.75 —
—
VOL IOL = 2 mA — — VDDIO1 x 0.15
V
V
Si5340 Status Output Pins (INTR), LOL, LOS_XAXB, SDA/SDIO2, SDO
Output Voltage
VOH
IOH = –2 mA VDDIO1 x 0.75 —
—
VOL IOL = 2 mA — — VDDIO1 x 0.15
V
V
Notes:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Refer to the Reference Manual for more
details on register settings.
2. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is
unused with I2C_SEL pulled high. VOL remains valid in all cases.
Rev. 1.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet Si5340.PDF ] | |
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