Si5341 Datasheet PDF - Silicon Laboratories
| Part Number | Si5341 | |
| Description | CLOCK GENERATOR | |
| Manufacturers | Silicon Laboratories | |
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Si5341/40
L OW- J ITTER, 1 0 - O UTPUT, A NY- F REQUENCY, A NY- O UTPUT
CLOCK GENERATOR
Features
Generates up to 10 independent
DCO mode with frequency steps as
output clocks
low as 0.001 ppb
Ultra-low jitter: <100 fs RMS typical Independent output clock supply pins:
MultiSynth™ technology enables any- 3.3 V, 2.5 V, or 1.8 V
frequency synthesis on any-output Built-in power supply filtering and
Highly configurable outputs
regulation
compatible with LVDS, LVPECL, CML, Status monitoring: LOS, LOL
LVCMOS, HCSL, or programmable Serial Interface: I2C or SPI (3-wire or
voltage
4-wire)
Input frequency range:
User programmable (2x) non-volatile
External crystal: 25, 48-54 MHz
OTP memory
Differential clock: 10 to 750 MHz
LVCMOS clock: 10 to 250 MHz
Output frequency range:
Differential: 100 Hz to 712.5 MHz
LVCMOS: 100 Hz to 250 MHz
Output-output skew: 20 ps typ
Adjustable output-output delay
Optional zero delay mode
Independent glitchless on-the-fly
output frequency changes
ClockBuilderTM Pro software utility
simplifies device configuration and
assigns customer part numbers
Si5341: 4 input, 10 output, compact
9x9 mm, 64 QFN
Si5340: 4 input, 4 output, compact
7x7 mm, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Device Selector Guide
Grade
Si534xA
Si534xB
Si534xC
Si534xD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Mode
Integer + Fractional
Integer Only
Applications
9x9 mm
7x7 mm
Ordering Information
See Section 8.
Functional Block Diagram
Si5341/40
IN_SEL[1:0]
IN0 ÷INT
IN1 ÷INT
IN2 ÷INT
XA
XB
FB_IN
OSC
÷INT
PLL
Clock tree generation replacing XOs,
buffers, signal format translators
Any-frequency clock translation
Clocking for FPGAs, processors,
memory
Ethernet switches/routers
OTN framers/mappers/processors
Test equipment & instrumentation
Broadcast video
Description
The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL
with proprietary MultiSynth fractional synthesizer technology to offer a versatile and
high performance clock generator platform. This highly flexible architecture is capable
of synthesizing a wide range of integer and non-integer related frequencies up to
712.5 MHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter
performance with 0 ppm error. Each of the clock outputs can be assigned its own
format and output voltage enabling the Si5341/40 to replace multiple clock ICs and
oscillators with a single device making it a true “clock tree on a chip”.
The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software.
Custom part numbers are automatically assigned using a ClockBuilder Pro for fast,
free, and easy factory pre-programming, or the Si5341/40 can be programmed in-
circuit via I2C and SPI serial interfaces.
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
NVM
I2C/SPI
Control/
Status
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si5341/40
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Si5341/40
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%,TA = –40 to 85 °C)
Parameter
Ambient Temperature
Junction Temperature
Core Supply Voltage
Output Driver Supply Voltage
Symbol
TA
TJMAX
VDD
VDDA
VDDO
Min
–40
—
1.71
3.14
3.14
2.38
Typ
25
—
1.80
3.30
3.30
2.50
Max Units
85 °C
125 °C
1.89 V
3.47 V
3.47 V
2.62 V
1.71 1.80 1.89
V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Rev. 1.0
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ Si5341.PDF Datasheet ] | |
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