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What is 54ACT715?

This electronic component, produced by the manufacturer "National Semiconductor", performs the same function as "Programmable Video Sync Generator".


54ACT715 Datasheet PDF - National Semiconductor

Part Number 54ACT715
Description Programmable Video Sync Generator
Manufacturers National Semiconductor 
Logo National Semiconductor Logo 


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December 1998
LM188254ACT715
LM1882-R54ACT715-R Programmable Video Sync
Generator
General Description
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin
TTL-input compatible devices capable of generating Hori-
zontal, Vertical and Composite Sync and Blank signals for
televisions and monitors. All pulse widths are completely de-
finable by the user. The devices are capable of generating
signals for both interlaced and noninterlaced modes of op-
eration. Equalization and serration pulses can be introduced
into the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the system
architecture. Line rate and field/frame rate are all a function
of the values programmed into the data registers, the status
register, and the input clock frequency.
The ’ACT715/LM1882 is mask programmed to default to a
Clock Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming be-
fore operation.
The ’ACT715-R/LM1882-R is the same as the ’ACT715/
LM1882 in all respects except that the ’ACT715-R/
LM1882-R is mask programmed to default to a Clock En-
abled state. Bit 10 of the Status Register defaults to a logic
“1”. Although completely (re)programmable, the ’ACT715-R/
LM1882-R version is better suited for applications using the
default 14.31818 MHz RS-170 register values. This feature
allows power-up directly into operation, following a single
CLEAR pulse.
Features
n Maximum Input Clock Frequency > 130 MHz
n Interlaced and non-interlaced formats available
n Separate or composite horizontal and vertical Sync and
Blank signals available
n Complete control of pulse width via register
programming
n All inputs are TTL compatible
n 8 mA drive on all outputs
n Default RS170/NTSC values mask programmed into
registers
n 4 KV minimum ESD immunity
n ’ACT715-R/LM1882-R is mask programmed to default to
a Clock Enable state for easier start-up into
14.31818 MHz RS170 timing
Connection Diagrams
Pin Assignment for
DIP and SOIC
Pin Assignment
for LCC
DS100232-1
Order Number LM1882CN or LM1882CM
For Default RS-170, Order Number
LM1882-RCN or LM1882-RCM
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100232
DS100232-2
www.national.com

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54ACT715 equivalent
Signal Specification (Continued)
DS100232-5
FIGURE 2. Vertical Waveform Specification
FIGURE 3. Equalization/Serration Interval Programming
DS100232-12
HORIZONTAL AND VERTICAL GATING SIGNALS
Horizontal Drive and Vertical Drive outputs can be utilized as
general purpose Gating Signals. Horizontal and Vertical Gat-
ing Signals are available for use when Composite Sync and
Blank signals are selected and the value of Bit 2 of the Sta-
tus Register is 0. The Vertical Gating signal will change in the
same manner as that specified for the Vertical Blank.
Horizontal Gating Signal Width = [REG(16) − REG(15)] x
ckper
Vertical Gating Signal Width: = [REG(18) − REG(17)] x
hper
CURSOR POSITION AND VERTICAL INTERRUPT
The Cursor Position and Vertical Interrupt signal are avail-
able when Composite Sync and Blank signals are selected
and Bit 2 of the Status Register is set to the value of 1. The
Cursor Position generates a single pulse of n clocks wide
during every line that the cursor is specified. The signals are
generated by logically ORing (ANDing) the active LOW
(HIGH) signals specified by the registers used for generating
Horizontal and Vertical Gating signals. The Vertical Interrupt
signal generates a pulse during the vertical interval speci-
fied. The Vertical Interrupt signal will change in the same
manner as that specified for the Vertical Blanking signal.
Horizontal Cursor Width = [REG(16) − REG(15)] x ckper
Vertical Cursor Width = [REG(18) − REG(17)] x hper
Vertical Interrupt Width = [REG(14) − REG(13)] x hper
Addressing Logic
The register addressing logic is composed of two blocks of
logic. The first is the address register and counter (AD-
DRCNTR), and the second is the address decode (AD-
DRDEC).
ADDRCNTR LOGIC
Addresses for the data registers can be generated by one of
two methods. Manual addressing requires that each byte of
each register that needs to be loaded needs to be ad-
dressed. To load both bytes of all 19 registers would require
a total of 57 load cycles (19 address and 38 data cycles).
Auto Addressing requires that only the initial register value
be specified. The Auto Load sequence would require only 39
load cycles to completely program all registers (1 address
and 38 data cycles). In the auto load sequence the low order
byte of the data register will be written first followed by the
high order byte on the next load cycle. At the time the High
Byte is written the address counter is incremented by 1. The
counter has been implemented to loop on the initial value
loaded into the address register. For example: If a value of 0
was written into the address register then the counter would
count from 0 to 18 before resetting back to 0. If a value of 15
was written into the address register then the counter would
count from 15 to 18 before looping back to 15. If a value
greater than or equal to 18 is placed into the address register
the counter will continuously loop on this value. Auto ad-
dressing is initiated on the falling edge of LOAD when AD-
DRDATA is 0 and LHBYTE is 1. Incrementing and loading of
data registers will not commence until the falling edge of
LOAD after ADDRDATA goes to 1. The next rising edge of
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Featured Datasheets

Part NumberDescriptionMFRS
54ACT715The function is Programmable Video Sync Generator. National SemiconductorNational Semiconductor
54ACT715-RThe function is Programmable Video Sync Generator. National SemiconductorNational Semiconductor

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