PDF HYB25DC256163CE-6 Data sheet ( Hoja de datos )

Número de pieza	HYB25DC256163CE-6
Descripción	256-Mbit Double-Data-Rate SGRAM
Fabricantes	Qimonda
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No Preview Available ! HYB25DC256163CE-4 HYB25DC256163CE-5 HYB25DC256163CE-6 256-Mbit Double-Data-Rate SGRAM Green Product January 2007 Internet Data Sheet Rev. 1.1 1 page Internet Data Sheet HYB25DC256163CE 256-Mbit Double-Data-Rate SGRAM 2 Chip Configuration The chip configuration of a DDR SGRAM is listed by function in Table 3. The abbreviations used in the Pin#/Buffer# column are explained in Table 4 and Table 5 respectively. The chip numbering for TSOP is depicted in Figure 1. Ball# Name Clock Signals 45 CK 46 CK 44 CKE Control Signals 23 RAS 22 CAS 21 WE 24 CS Address Signals 26 BA0 27 BA1 29 A0 30 A1 31 A2 32 A3 35 A4 36 A5 37 A6 38 A7 39 A8 40 A9 28 A10 AP 41 A11 42 A12 NC 17 A13 NC Pin Type Buffer Type I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL I SSTL NC — I SSTL NC — Function Clock Signal Complementary Clock Signal Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Select Bank Address Bus 2:0 Address Bus 11:0 TABLE 3 Chip Configuration Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: Module based on 128 Mbit or smaller dies Address Signal 13 Note: 1 Gbit based module Note: Module based on 512 Mbit or smaller dies Rev. 1.1, 2007-01 03292006-SR4U-HULB 5 5 Page Internet Data Sheet HYB25DC256163CE 256-Mbit Double-Data-Rate SGRAM %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ 23(5$7,1*02'( '6 '// 03%' Field DLL Bits 0 Type1) W DS 1 MODE [12:2] 1) W = write only register bit Description DLL Status 0B Enabled 1B Disabled Drive Strength 0B Normal 1B Weak Operating Mode Note: All other bit combinations are RESERVED. 00000000000B Normal Operation TABLE 7 Truth Table 1a: Commands Name (Function) CS RAS CAS WE Address MNE Note Deselect (NOP) H X X XX NOP 1)2) No Operation (NOP) L H H HX NOP 1)2) Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1)3) Read (Select Bank And Column, And Start Read Burst) LH L H Bank/Col Read 1)4) Write (Select Bank And Column, And Start Write Burst) LH L L Bank/Col Write 1)4) Burst Terminate L H H LX BST 1)5) Precharge (Deactivate Row In Bank Or Banks) L L H L Code PRE 1)6) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L HX AR/SR 1)7)8) Mode Register Set LL L L Op-Code MRS 1)9) 1) CKE is HIGH for all commands shown except Self Refresh. VREF must be maintained during Self Refresh operation 2) Deselect and NOP are functionally interchangeable. 3) BA0-BA1 provide bank address and A0-A12 provide row address. 4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16);A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. 5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts. 6) A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”. 7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW. 8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE. 9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register). Rev. 1.1, 2007-01 03292006-SR4U-HULB 11 11 Page

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