71M6545 Datasheet PDF - Maxim Integrated
Part Number | 71M6545 | |
Description | Metrology Processors | |
Manufacturers | Maxim Integrated | |
Logo | ||
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Metrology Processors
GENERAL DESCRIPTION
The 71M6545/71M6545H metrology processors are based on
4th-generation metering architecture supporting the 71M6xxx
series of isolated current sensing products that offer drastic
reduction in component count, immunity to magnetic tampering,
and unparalleled reliability. The 71M6545/71M6545H integrate
our Single Converter Technology® with a 22-bit delta-sigma
ADC, a customizable 32-bit computation engine (CE) for core
metrology functions, as well as a user-programmable 8051-
compatible application processor (MPU) core with up to 64KB
flash and up to 5KB RAM.
An external host processor can access metrology functions di-
rectly through the SPI™ interface, or alternatively through the
embedded MPU core in applications requiring metrology data
capture, storage, and preprocessing within the metrology
subsystem. In addition, the devices integrate an RTC, DIO, and
UART. A complete array of ICE and development tools,
programming libraries, and reference designs enable rapid
development and certification of meters that meet all ANSI and
IEC electricity metering standards worldwide.
C Shunt Resistor Sensors
NEUTRAL
B
A
LOAD
HOST
POWER SUPPLY
This system is referenced to Neutral
NEUTRAL
Pulse Transformers
C
B
A
SPI_CKI
SPI_DI
SPI_DO
SPI_CSZ
XFER_BUSY
SAG
MUX and ADC
IADC0
IADC1
} IN*
VADC10 (VC)
IADC6
IADC7
}
IC
VADC9 (VB)
IADC4
IADC5
}
IB
VADC8(VA)
IADC2
IADC3
} IA
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
71M6545/H
PB
REGULATOR
TEMPERATURE
SENSOR
VBAT_RTC
BATTERY
MONITOR
VREF
SERIAL PORT
RX
TX
FLASH
MEMORY
RAM
MPU
RTC
TIMERS
OSCILLATOR/
PLL XIN
XOUT
DIO, PULSES,
LEDs
DIO
ICE
T
SPI INTERFACE
M
U
COMPUTE
ENGINE
X
V3P3D
WPULSE
XPULSE
RPULSE
YPULSE
10/7/2010
RTC
BATTERY
32 kHz
24
DIO
I2C or µWire
EEPROM
PULSES 3.3 VDC
*IN = Optional Neutral Current
FEATURES
• 0.1% Typical Accuracy Over 2000:1
Current Range
• Exceeds IEC 62053/ANSI C12.20 Standards
• Seven Sensor Inputs with Neutral Current
Measurement, Differential Mode Selectable
for Current Inputs
• Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
• High-Speed Wh/VARh Pulse Outputs with
Programmable Width
• Flash/RAM Size
32KB/3KB (71M6545)
64KB/5KB (71M6545H)
• Up to Four Pulse Outputs with Pulse Count
• Four-Quadrant Metering, Phase
Sequencing
• Digital Temperature Compensation
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Crystal in All Power Modes
• Independent 32-Bit Compute Engine
• 46–64Hz Line Frequency Range with the
Same Calibration
• Phase Compensation (±7°)
• 1µA Supply Current in Sleep Mode
• Flash Security
• In-System Program Update
• 8-Bit MPU (80515), Up to 5 MIPS, for
Optional Implementation of Postprocessing
and Host Support Functions (Optional Use)
• Up to 29 DIO Pins
• Hardware Watchdog Timer (WDT)
• I2C/MICROWIRE® EEPROM Interface
• SPI Interface for Host:
Full Access to Shared Memory Space
Flash Program Capability
• UART
• Industrial Temperature Range
• 64-Pin Lead(Pb)-Free LQFP Package
Single Converter Technology is a registered trademark of Maxim Integrated Products, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct at
19-5378; Rev 2; 10/13
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
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71M6545/71M6545H Data Sheet
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 9
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes)......................................................... 12
Figure 3. AFE Block Diagram (Four CTs) ................................................................................................... 13
Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) ..................................................................... 17
Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) ..................................................................... 17
Figure 6: General Topology of a Chopped Amplifier .................................................................................. 20
Figure 7: CROSS Signal with CHOP_E = 00............................................................................................... 21
Figure 8: RTM Timing ................................................................................................................................. 26
Figure 9. Pulse Generator FIFO Timing...................................................................................................... 28
Figure 10: Samples from Multiplexer Cycle (Frame) .................................................................................. 29
Figure 11: Accumulation Interval ................................................................................................................ 29
Figure 12: Interrupt Structure ...................................................................................................................... 45
Figure 13: Automatic Temperature Compensation..................................................................................... 52
Figure 14: Connecting an External Load to DIO Pins................................................................................. 57
Figure 15: 3-wire Interface. Write Command, HiZ=0. ................................................................................ 59
Figure 16: 3-wire Interface. Write Command, HiZ=1 ................................................................................. 59
Figure 17: 3-wire Interface. Read Command............................................................................................. 59
Figure 18: 3-Wire Interface. Write Command when CNT=0...................................................................... 59
Figure 19: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................... 59
Figure 20: SPI Slave Port - Typical Multi-Byte Read and Write operations................................................ 61
Figure 21: Voltage, Current, Momentary and Accumulated Energy ........................................................... 66
Figure 22: Data Flow................................................................................................................................... 69
Figure 23: Resistive Voltage Divider (Voltage Sensing) ............................................................................. 71
Figure 24. CT with Single-Ended Input Connection (Current Sensing) ...................................................... 71
Figure 25: CT with Differential Input Connection (Current Sensing) .......................................................... 71
Figure 26: Differential Resistive Shunt Connections (Current Sensing)..................................................... 71
Figure 27: System Using Three-Remotes and One-Local (Neutral) Sensor .............................................. 72
Figure 28. System Using Current Transformers ......................................................................................... 73
Figure 29: I2C EEPROM Connection .......................................................................................................... 79
Figure 30: Connections for the UART......................................................................................................... 79
Figure 31: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right)........ 80
Figure 32: External Components for the Emulator Interface ...................................................................... 80
Figure 33. Trim Fuse Bit Mapping............................................................................................................... 98
Figure 34: CE Data Flow: Multiplexer and ADC........................................................................................ 111
Figure 35: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase......................... 111
Figure 36: CE Data Flow: Squaring and Summation Stages.................................................................... 112
Figure 37: 64-pin LQFP Package Outline ................................................................................................. 125
Figure 38: Pinout for the LQFP-64 Package............................................................................................. 126
Figure 39: I/O Equivalent Circuits ............................................................................................................. 130
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