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PDF 74VHCT125 Data sheet ( Hoja de datos )

Número de pieza 74VHCT125
Descripción Quad buffer/line driver
Fabricantes NXP Semiconductors 
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No Preview Available ! 74VHCT125 Hoja de datos, Descripción, Manual

74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
Rev. 02 — 13 October 2009
Product data sheet
1. General description
The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard JESD7-A.
The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH
at nOE causes the outputs to assume a high-impedance OFF-state.
The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active
LOW enable inputs.
2. Features
I Balanced propagation delays
I All inputs have a Schmitt-trigger action
I Inputs accepts voltages higher than VCC
I Input levels:
N The 74VHC125 operates with CMOS logic levels
N The 74VHCT125 operates with TTL logic levels
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Multiple package options
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
74VHC125D
74VHCT125D
40 °C to +125 °C SO14
plastic small outline package; 14 leads;
body width 3.9 mm
74VHC125PW 40 °C to +125 °C
74VHCT125PW
TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
74VHC125BQ 40 °C to +125 °C
74VHCT125BQ
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Version
SOT108-1
SOT402-1
SOT762-1

1 page




74VHCT125 pdf
NXP Semiconductors
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
CI input
capacitance
CO output
capacitance
For type 74VHCT125
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
VOH
VOL
IOZ
II
ICC
ICC
CI
HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 µA
IO = 8.0 mA
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 µA
IO = 8.0 mA
OFF-state
per input pin; VI = VIH or VIL;
output current VCC = 5.5 V; IO = 0 A
VO = VCC or GND;
other pins at VCC or GND
input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
per input pin;
supply current VI = VCC 2.1 V; IO = 0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
input
capacitance
CO output
capacitance
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
- 3.0 10
-
10
-
10 pF
- 4.0 -
-
-
-
- pF
2.0 - - 2.0
-
2.0
-V
- - 0.8 -
0.8
-
0.8 V
4.4 4.5 -
4.4
-
4.4
-V
3.94 - - 3.8 - 3.70 - V
- 0 0.1 -
0.1
-
0.1 V
- - 0.36 -
0.44
-
0.55 V
- - ±0.25 - ±2.5 - ±10.0 µA
- - 0.1 -
1.0
-
2.0 µA
- - 2.0 -
20
-
40 µA
- - 1.35 -
1.5
-
1.5 mA
- 3.0 10
-
10
-
10 pF
- 4.0 -
-
-
-
- pF
74VHC_VHCT125_2
Product data sheet
Rev. 02 — 13 October 2009
© NXP B.V. 2009. All rights reserved.
5 of 15

5 Page





74VHCT125 arduino
NXP Semiconductors
74VHC125; 74VHCT125
Quad buffer/line driver; 3-state
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
y
Z
14
8
c
EA
X
HE v M A
pin 1 index
1
e
7
bp
wM
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
5.1
4.9
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT402-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13 0.1
0.72
0.38
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 10. Package outline SOT402-1 (TSSOP14)
74VHC_VHCT125_2
Product data sheet
Rev. 02 — 13 October 2009
© NXP B.V. 2009. All rights reserved.
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