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PDF SPMC01A Data sheet ( Hoja de datos )
| Número de pieza | SPMC01A | |
| Descripción | Microcontroller | |
| Fabricantes | Sunplus | |
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SPMC01A
Microcontroller
SEP. 21, 2001
Version 1.4
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
1 page  
SPMC01A
5. FUNCTIONAL DESCRIPTIONS
5.1. CPU
The microprocessor of SPMC01A is a SUNPLUS high
performance processor equipped with Accumulator, Program
Counter, X Register, Stack Pointer and Processor Status Register
(The same as 6502 instruction‘s structure). SPMC01A is a fully
static CMOS design. The oscillation frequency could be varied
up to 6.0MHz depends on the application needs. The SPMC01A
development system includes a SUNPLUS ICE, Evaluation Chip
and Engineering Development Board.
5.1.1. Processor status register
Bit 7 6 5 4 3 2 1 0
Flag N
V
-
B
-
I ZC
N: Negative, V: Overflow, B: Brk command, I: IRQ disable, Z: Zero, C: Carry
5.1.2. Block diagram of SUNPLUS CPU
REGISTER SECTION
A0
A1
A2
A3
A4
A5
A6
A7
ADDRESS
BUS
INDEX
REGISTER
X
STACK POINT
REGISTER
S
ALU
ACCUMULATOR
A
A8
A9
A10
A11
A12
A13
A14
A15
LEGEND
= 8BIT LINE
PCL
PCH
INPUT DATA
LATCH
IDLI
DATA BUS
BUFFER
= 1 BIT LINE
CONTROL SECTION
RESET IRQ NMI
INTERRUPT
LOGIC
INSTRUCTION
DECODE
RDY
PD
TIMING
CONTROL
PROCESSOR
STATUS
REGISTER
P
CLOCK
GENERATOR
CLK 0 IN
INSTRUCTION
REGISTER
R/W
D0
DDDDDDD1234567
DATA
BUS
5.2. Memory
5.2.1. Memory map
$0000
I/O Registers
$000A
$000B
$00BF
$00C0
$00FF
$0400
$05FF
$0600
$0FFF
Not used
User SRAM
64 bytes
Reserved for test
0.5K bytes ROM
Program ROM
2.5K bytes
5.2.2. RAM
Total of sixty-four bytes of RAM (including the stack) is available
from $00C0 to $00FF. The stack begins at address $00FF and
proceeds down to $00C0.
5.2.3. ROM
Total of 3072 bytes of on-chip ROM including 2560 bytes of user
ROM located from $0600 through $0FFF and 512 bytes of internal
test ROM located from $0400 through $05FF. Users‘ program
can only be allocated $0600 through $0FFF (2.5K).
5.2.4. NMI, RESET, IRQ vectors
The address of NMI (not provided in this chip), RESET and IRQ
are located from $0FFA to $0FFF. The interrupt vectors should
be specified in the program as follows:
ORG $0FFA
;define SPMC01A chip
;interrupt vector.
DW NMI_ROUTINE
DW RESET
DW INT_ROUTINE
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
5
SEP. 21, 2001
Version: 1.4
5 Page 
SPMC01A
the RTI circuit and further dividing it by eight (RT1, RT0 timing
times 8). This time out generates reset if the WDT register is not
clear. An internal reset is generated and reset vector is fetched.
Preventing a WDT time-out reset is done by writing a ‘1’ to WDT
($0007 b0) within a specific time. The min. WDT reset times
listed in (RT1, RT0) & WDT Interrupt Frequency Table.
Addr
Register
R/W 7
6
5
4
3
2
1
0 Enable
$0007 WATCH DOG
R
WDT TIMER STATUS
W
WDT(0) 1 = CLR
Example: Clear Watch-Dog Timer
MainPGMLoop:
JSR Clear_WDT
....
;Long program will over
;Watch-Dog Timer
JSR Clear_WDT ;so need call clear WDT
;subroutine again.
....
JMP MainPGMLoop
Clear_WDT:
LDA #01h
STA WDT
;WDT ($0007), clear
;$0007 B0 WDT register.
RTS
5.7.4. Illegal address reset (IAR) (see Appendix E)
The internal reset of IAR generated when an instruction opcode
fetch occurs from an address not implemented in the RAM
($00C0-$00FF) nor ROM ($0400-$0FFF). The IAR will generate
the reset signal that will reset the CPU and other peripherals.
5.7.5. Low voltage reset (LVR) (see Appendix E)
The internal LVR reset generated when VDD falls below the
specified LVR trigger voltage value (2.2 volt.) at least one CPU
clock cycle.
5.8. Interrupt - see Appendix A, B, F, G
(Interrupt Diagram)
5.8.1. Software interrupt (BRK)
The BRK is an executable instruction interrupt since it executed
regardless of the state of the I-bit in the processor status register
flag (inside CPU). When BRK occurred, jump to IRQ_routine.
As with any instruction, interrupts pending during the previous
instruction is served.
5.8.2. External interrupt
The External interrupt sources include IRQ pin, PA3 - 0 and PA7.
The IRQ pins provide an asynchronous interrupt to the CPU by
program control. The PA3-0 can be mask option as an external
interrupt. PA7 can be programmed as an external interrupt, not
by mask option. The PA7 and IRQ pin are designed with Schmitt
Trigger input and low active, but PA3 - 0 are high active.
Addr
Register
$0006 IRQ CONTROL &
IRQS STATUS
R/W 7
R 0(0)
W IRQR1
6
0(0)
IRQR
5
0
4 3 2 1 0 Enable
0 IRQF(0) IRQF1(0) IRQE1 IRQE
(0) (0) 1 = SET
5.8.3. IRQ, PA3 - 0 interrupt (see Appendix A, F, G)
The IRQ/PB5 pin can be selected to I/O or I/O with IRQ by
program. When IRQ function is selected, the IRQ pin is the main
external source of an interrupt with active-low polarity. This pin is
connected to a Schmitt trigger input. Since it is an open-drain
mode, it needs to be pulled-up externally. When PB5 I/O function
is selected, PB5 is normal I/O with open-drain always. When
IRQE1 is disabled, the interrupt flag of IRQ, IRQF, will be cleared
during creating interrupt. However, if IRQE1 is enabled, the
IRQF will not be cleared by interrupt. This interrupt source can be
either " Edge-Trigger" or "Level-Trigger". It is selected by mask
option. If mask option is set to “Edge-Trigger” mode, the following
conditions will cause IRQ interrupt:
1). Falling edge on the IRQ pin.
2). Rising edge on any of PA3 - 0 pin. (If PA3 - 0 is mask option
enabled.)
If mask option is set to “Edge-Level Trigger” mode, the following
conditions will cause IRQ interrupt:
1). Falling edge and Low level trigger on the IRQ pin.
2). Rising edge and High level on any one of PA3 - 0 pin. (If PA3 -
0 is mask option enabled.)
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
11
SEP. 21, 2001
Version: 1.4
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