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PDF LT8495 Data sheet ( Hoja de datos )
| Número de pieza | LT8495 | |
| Descripción | SEPIC/Boost Converter | |
| Fabricantes | Linear Technology Corporation | |
| Logotipo |  |
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LT8495
Features
SEPIC/Boost Converter with
2A, 70V Switch, 9µA Quiescent
Current, POR and Watchdog Timer
Description
n Wide Input Voltage Range of ~1V to 60V
(2.5V to 32V for Start-Up)
n Low Ripple Burst Mode® Operation
n 9µA IQ at 12VIN to 5.0VOUT
n Output Ripple (<10mV Typ.)
n Dual Supply Pins:
n Improves Efficiency
n Reduces Minimum Supply Voltage to ~1V after
Start-Up to Extend Battery Life
n Integrated 2A/70V Power Switch
n Programmable Watchdog Timer Can Operate When
VIN Supply Is Removed
n Programmable Power-On Reset Timer (POR) with
RST Functional for Input Supply Down to 1.3V
n FMEA Fault Tolerant in TSSOP Package
n Fixed Frequency PWM, SEPIC/BOOST/FLYBACK
Topologies
n Programmable Switching Frequency:
250kHz to 1.5MHz
n UVLO Programmable on SWEN and RSTIN Pins
n Soft-Start Programmable with One Capacitor
n 20-Lead TSSOP Package
Applications
n Automotive ECU Power
n Power for Portable Products
n Industrial Supplies
TheLT®8495isanadjustablefrequency (250kHzto 1.5MHz)
monolithic switching regulator with a power-on reset and
watchdog timer. Quiescent current can be less than 9µA
when operating and is ~0.3µA when SWEN, WDE and RSTIN
are low. Configurable as a SEPIC, boost or flyback con-
verter, the low ripple Burst Mode operation maintains high
efficiency at low output current while keeping output
ripple below 10mV. Dual supply pins (VIN and BIAS) allow
the part to automatically operate from the most efficient
supply. Input supply voltage can be up to 60V for SEPIC
topologies and up to 32V (with ride-through up to 60V)
for boost and flyback topologies. After start-up, battery
life is extended since the part can draw current from its
output (BIAS) even when VIN voltage drops below 2.5V.
The reset and watchdog timeout periods are independently
adjustable using external capacitors. Using a resistor divider
on the SWEN pin provides a programmable undervoltage
lockout (UVLO) for the converter. A resistor divider connected
to RSTIN provides UVLO control that asserts the RST pin.
Additional features such as frequency foldback and soft-
start are integrated. Fault tolerance in the TSSOP allows
for adjacent pin shorts or an open without raising the
output voltage above its programmed value. The LT8495
is available in a 20-lead TSSOP package with exposed
pads for low thermal resistance.
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
450kHz, 5V Output SEPIC Converter
VIN
3V TO 60V
2.2µF
• 15µH
2.2µF
15µH
•
1nF
4.7nF
1µF
169k
SW BIAS
VIN
SWEN
RSTIN
FB
LT8495
CWDT
CPOR
GND
SS WDO
RT WDE
RST
WDI
1M 4.7pF
8.87k
316k
47µF
×2
VOUT
5V
0.35A (VIN = 3V)
0.6A (VIN = 5V)
1.0A (VIN >12V)
µC
8495 TA01a
No-Load Supply Current
25
20
15
10
WATCHDOG ENABLED
5
WATCHDOG DISABLED
0
0 12 24 36 48 60
INPUT VOLTAGE (V)
8495 TA01b
For more information www.linear.com/LT8495
90
85
80
75
70
65
60
0.0
Efficiency
VIN = 5V
VIN = 24V
VIN = 12V
0.2 0.4 0.6 0.8
LOAD CURRENT (A)
1.0
8495 TA01c
8495f
1
1 page  
LT8495
Typical Performance Characteristics TA = 25°C, unless otherwise noted.
No Load Supply Current
100
FRONT PAGE APPLICATION
VIN=12V
80
60
40
20
0
–50 –10
30
70 110 150
TEMPERATURE (°C)
8495 G01
Switching Waveforms,
Burst Mode Operation
Maximum Load Current
2.5
FRONT PAGE APPLICATION
2.0
TYPICAL
1.5
1.0
MINIMUM
0.5
0.0
0
12 24 36 48 60
VIN (V)
8495 G02
Switching Waveforms, Full
Frequency Continuous Operation
Load Regulation
0.15
0.10
0.05
–0.00
–0.05
–0.10 VIN=12V
FRONT PAGE APPLICATION
–0.15 REFERENCED TO VOUT AT 100mA LOAD
0 200 400 600 800
1000
LOAD CURRENT (mA)
LT8495 G03
Transient Load Response; Load
Current Is Stepped from 300mA
to 500mA
VSW
10V/DIV
IL
0.5A/DIV
VOUT
5mV/DIV
VSW
10V/DIV
IL
0.5A/DIV
VOUT
5mV/DIV
VOUT
50mV/DIV
IL
0.5A/DIV
10ms/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
ILOAD = 20mA
8495 G04
Transient Load Response; Load
Current Is Stepped from 20mA
(Burst Mode Operation) to 220mA
VOUT
100mV/DIV
IL
0.5A/DIV
500µs/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
8495 G07
1µs/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
ILOAD = 0.5A
8495 G05
Switch Current Limit at 500kHz
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10 20 30 40 50 60 70 80 90
DUTY CYCLE (%)
8495 G08
For more information www.linear.com/LT8495
500µs/DIV
FRONT PAGE APPLICATION
VIN = 12V
VOUT = 5V
8495 G06
Switch Current Limit at Minimum
Duty Cycle
3.0
2.5
2.0
1.5
1.0
0.5
0.0
–50
0 50 100
TEMPERATURE (°C)
150
8495 G09
8495f
5
5 Page 
LT8495
Operation
The LT8495 is a constant-frequency, current mode
SEPIC/boost/flyback regulator with power-on reset and
a watchdog timer. Operation can be best understood by
referring to the Block Diagram. The switching regulation,
watchdog timer and reset detection functions are con-
trolled by the SWEN, WDE and RSTIN pins respectively. If
all three pins are grounded, the part enters shutdown with
minimal current drawn from the VIN and BIAS sources. If
any of these three pins are driven above their respective
thresholds, this part is turned on.
Switching Regulator Operation
In the Block Diagram, the adjustable oscillator, with fre-
quency set by the external RT resistor, enables an RS latch,
turning on the internal power switch. An amplifier and
comparator monitor the switch current flowing through
an internal sense resistor, turning the switch off when this
current reaches a level determined by the voltage at VC.
An error amplifier adjusts the VC voltage by measuring
the output voltage through an external resistor divider
tied to the FB pin. If the error amplifier’s output voltage
(VC) increases, more current is delivered to the output;
if the VC voltage decreases, less current is delivered. An
active clamp on the VC voltage provides current limit. An
internal regulator provides power to the control circuitry.
In order to improve efficiency, the NPN power switch
driver (see Block Diagram) supplies NPN base current
from whichever of VIN and BIAS has the lower supply
voltage. However, if either of them is below 2.4V or above
34V (typical values), the power switch draws current from
the other pin. If both supply pins are below 2.4V or above
34V then switching activity is stopped.
To further optimize efficiency, the LT8495 automatically
enters Burst Mode operation in light load situations. Be-
tween bursts, all circuitry associated with controlling the
output switch is shut down, reducing the VIN/BIAS pin
supply currents to be less than 3µA to 6µA typically (see
Electrical Characteristics table).
Start-Up Operation
Several functions are provided to enable a very clean
start-up for the LT8495.
• First, the SWEN pin voltage is monitored by an internal
voltage reference to give a precise turn-on threshold.
An external resistor divider can be connected from the
input power supply to the SWEN pin to provide a user-
programmable undervoltage lock-out function.
• Second, the soft-start circuitry provides for a gradual
ramp-up of the switch current. When the part is brought
out of shutdown, the external SS capacitor is first dis-
charged, and then an integrated 256k resistor pulls the
SS pin up to ~2.1V. By connecting an external capacitor
to the SS pin, the voltage ramp rate on the pin can be
set. Typical values for the soft-start capacitor range
from 100nF to 1µF.
• Finally, the frequency foldback circuit reduces the
maximum switching frequency when the FB pin is below
1V. This feature reduces the minimum duty cycle that
the part can achieve thus allowing better control of the
switch current during start-up.
Power-On Reset and Watchdog Timer Operation
The LT8495 has a power-on reset (POR) circuit and a reset
timer to assert the RST pin for a minimum amount of time.
After initial power up the open-drain RST pin is asserted
low for a programmable reset delay time (see the Timing
Diagrams). During normal operation, the RST pin can also
be asserted when either the RSTIN pin is below its threshold
or the chip enters shutdown due to an abnormal condi-
tion. After the chip exits shutdown and the RSTIN pin rises
above its threshold, the RST pin is released after the reset
delay time which is programmable through the CPOR pin.
The watchdog timer typically monitors a microcontroller’s
activity. The watchdog timer can be enabled or disabled
by applying a logic signal to the WDE pin. When enabled,
the watchdog timer requires successive negative edges
on the WDI pin to happen within a programmed time win-
dow to keep WDO from pulsing low. Therefore, if the time
between the two negative WDI edges is too short or too
long, the WDO pin will be pulsed low. When the WDO pin
pulls low, a reset timer keeps the WDO pin low for a delay
programmed by the CPOR pin. The WDO pin will go high
again after the reset timer expires or the chip shuts down
(see the Timing Diagrams). The window periods can be
set through the CWDT pin.
8495f
For more information www.linear.com/LT8495
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LT8495.PDF ] | |
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