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What is TC74ACT373FW?

This electronic component, produced by the manufacturer "Toshiba Semiconductor", performs the same function as "OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT".


TC74ACT373FW Datasheet PDF - Toshiba Semiconductor

Part Number TC74ACT373FW
Description OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT
Manufacturers Toshiba Semiconductor 
Logo Toshiba Semiconductor Logo 


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TC74ACT373P/F/FW/FT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74ACT373P,TC74ACT373F,TC74ACT373FW,TC74ACT373FT
Octal D-Type Latch with 3-State Output
The TC74ACT373 is an advanced high speed CMOS OCTAL
LATCH with 3-STATE OUTPUT fabricated with silicon gate and
double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
These 8-bit D-type latches are controlled by a latch enable (LE)
and a output enable input ( OE ).
When the ( OE ) input is high, the eight outputs are in a high
impedance state.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: tpd = 5.2 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 8 μA (max) at Ta = 25°C
Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
Balanced propagation delays: tpLH ∼− tpHL
Pin and function compatible with 74F373
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74ACT373P
TC74ACT373F
TC74ACT373FW
TC74ACT373FT
Weight
DIP20-P-300-2.54A
: 1.30 g (typ.)
SOP20-P-300-1.27A
: 0.22 g (typ.)
SOP20-P-300-1.27
: 0.22 g (typ.)
SOL20-P-300-1.27
: 0.46 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
1 2006-06-01

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TC74ACT373FW equivalent
TC74ACT373P/F/FW/FT
AC Characteristics (CL = 50 pF, RL = 500 , input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(LE-Q)
Propagation delay
time
(D-Q)
Output enable time
Output disable time
Input capacitance
Output capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
CIN
COUT
CPD
Test Condition
VCC (V)
Ta = 25°C
Min Typ. Max
5.0 ± 0.5
5.8 9.2
5.0 ± 0.5
5.9 9.6
5.0 ± 0.5
6.5 10.5
5.0 ± 0.5
(Note)
5.5 7.8
5 10
10
32
Ta =
40 to 85°C
Min Max
1.0 10.5
1.0 11.0
1.0 12.0
1.0 9.0
10
――
――
Unit
ns
ns
ns
ns
pF
pF
pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per latch)
And the total CPD when n pcs. of F/F operate can be gained by the following equation:
CPD (total) = 20 + 12·n
5 2006-06-01


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Featured Datasheets

Part NumberDescriptionMFRS
TC74ACT373FThe function is OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT. Toshiba SemiconductorToshiba Semiconductor
TC74ACT373FTThe function is OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT. Toshiba SemiconductorToshiba Semiconductor
TC74ACT373FWThe function is OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT. Toshiba SemiconductorToshiba Semiconductor

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