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PDF W83195CG-413 Data sheet ( Hoja de datos )
| Número de pieza | W83195CG-413 | |
| Descripción | Clock Generator | |
| Fabricantes | Winbond | |
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Winbond Clock Generator
W83195WG-413
W83195CG-413
For ATI P4 Chipset
Date: Feb/27/2006 Revision: 0.6
1 page  
W83195WG-413/W83195CG-413
STEPLESS FOR ATI P4 CLOCK GENERATOR
1. GENERAL DESCRIPTION
The W83195WG-413/W83195CG-413 is a Clock Synthesizer for ATI P4 serial chipsets. W83195WG-
413/ W83195CG-413 provides all clocks required for the high-speed microprocessor and provides
step-less frequency programming and 32 different frequencies of CPU, PCI, and SRC clocks setting,
all clocks are externally selectable with smooth transitions.
The W83195WG-413/W83195CG-413 provides I2C serial bus interface to program the registers to
enable or disable each clock outputs and provides programmable S.S.T. scale to reduce EMI.
The W83195WG-413/W83195CG-413 accepts a 14.318 MHz reference crystal as its input and runs
on a 3.3V supply.
2. PRODUCT FEATURES
• 3 pair current-mode Differential clock outputs for CPU.
• 6 pair current-mode Differential clock outputs for SRC.
• 2 pair current-mode Differential clock outputs for ATIG programmable.
• 1 PCI clock output.
• 1 48 MHz clock output for USB.
• 3 14.318MHz REF clock outputs.
• Smooth frequency switch with selections from 100 to 400MHz.
• Step-less frequency programming.
• I2C 2-wire serial interface and support byte read/write and block read/write.
• Programmable S.S.T. scale to reduce EMI in M/N mode.
• Programmable registers to enable/disable each output and select modes.
• Programmable clock outputs slew rate control and skew control.
• 56 pin TSSOP/SSOP package.
Publication Release Date: Feb 2006
- 1 - Revision 0.6
5 Page 
3 Reserved
2 FS2_BACK
1 FS1_BACK
0 FS0_BACK
W83195WG-413/W83195CG-413
STEPLESS FOR ATI P4 CLOCK GENERATOR
X Reserved
X Power on latched value of FS2 pin. Default : 0
X Power on latched value of FS1 pin. Default : 0
X Power on latched value of FS0 pin. Default : 0
R
R
R
R
7.3 Register 2: ( Default : 03h )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
7 CLREQA7#_Ctr
6 CLREQA6#_Ctr
5 CLREQA5#_Ctr
4 CLREQA4#_Ctr
3 CLREQA3#_Ctr
2 CLREQA0#_Ctr
PWD
FUNCTION DESCRIPTION
SRCCLK7 is controlled by the CLREQA# pin
0 1: Controllable
0: Uncontrollable
SRCCLK6 is controlled by the CLREQA# pin
0 1: Controllable
0: Uncontrollable
SRCCLK5 is controlled by the CLREQA# pin
0 1: Controllable
0: Uncontrollable
SRCCLK4 is controlled by the CLREQA# pin
0 1: Controllable
0: Uncontrollable
SRCCLK3 is controlled by the CLREQA# pin
0 1: Controllable
0: Uncontrollable
SRCCLK0 is controlled by the CLREQA# pin
0 1: Controllable
0: Uncontrollable
1 Reserved
1 Reserved
0 Reserved
1 Reserved
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.4 Register 3: ( Default : 03h )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
7 CLREQB7#_Ctr
6 CLREQB6#_Ctr
PWD
FUNCTION DESCRIPTION
SRCCLK7 is controlled by the CLREQB# pin
0 1: Controllable
0: Uncontrollable
SRCCLK6 is controlled by the CLREQB# pin
0 1: Controllable
0: Uncontrollable
TYPE
R/W
R/W
Publication Release Date: Feb 2006
- 7 - Revision 0.6
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet W83195CG-413.PDF ] | |
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