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PDF uP6213 Data sheet ( Hoja de datos )
| Número de pieza | uP6213 | |
| Descripción | Multi-Phase Synchronous-Rectified Buck Controller | |
| Fabricantes | UPI Micro | |
| Logotipo |  |
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uP6213
Multi-Phase Synchronous-Rectified Buck Controller
for Next Generation CPU Core Power
General Description
Features
The uP6213A/B is a multi-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high-performance Intel microprocessors.
It integrates a 8-bit DAC that supports Intel VR10 and VR11
tables to set the output voltage between 0.5V and 1.6V.
The uP6213A provides programmable 3/4 phase operation.
The uP6213B provides programmable 1/2 phase operation.
The uP6213A/B also supports dynamic phase selection
by PS1/2/3 pins. Operation with phase reduction at light
load conditions achieves high efficiency over a wide range
of output current.
The uP6213A/B includes programmable no-load offset and
droop slope functions to adjust the output voltage as a
function of the load current, optimally positioning it for a
system transient.
Other features include accurate and reliable short-circuit
protection, adjustable over current protection, and a delayed
power OK output. The uP6213A is available in VQFN6x6-
40L package and uP6213B in VQFN4x4-28L package.
Ordering Information
Selectable Phase Number of Operation
uP6213A: 3/4 Phase
uP6213B: 1/2 Phase
8-bit DAC, Supporting Intel VR10 and VR11 CPUs
Programmable Dynamic Power Saving Mode
Operation
Simple Single-Loop Voltage-Mode Control
Lossless RDS(ON) Current Sensing for Current
Balance
Adjustable Operation Frequency form 50kHz to
1MHz Per Phase
External Compensation
Adjustable Over Current Protection
Adjustable Soft Start
VR_HOT and VR_RDY Indication
uP6213A in VQFN6x6 - 40L Package
uP6213B in VQFN4x4 - 28L Package
RoHS Compliant and 100% Lead (Pb)-Free
Order Number Package Type
Remark
Applications
uP6213AQAJ VQFN6x6 - 40L
uP6213BQJH VQFN4x4 - 28L
3/4 phase operation
1/2 phase operation
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 requirements. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.
Desktop PC Core Power Supplies
Middle/High End Graphic Cards
Low Output Voltage, High Power Density DC/DC
Converters
Voltage Regulator Modules
Pin Configuration
30 29 28 27 26 25 24 23 22 21
VOUT
TM
VR_HOT
PWM4
PWM3
PWM2
PWM1
NC
PS3
VID7
31
32
33
34
35
36
37
38
39
40
41
GND
20 CSN
19 CSP
18 COMP
17 FB
16 EAP
15 DAC
14 EN
13 PS2
12 GND
11 SS
1 2 3 4 5 6 7 8 9 10
21 20 19 18 17 16 15
VOUT
TB
PWM2
PWM1
VID6
VID5
VID4
22
23
24
25
26
27
28
29
GND
14 CSN
13 CSP
12 COMP
11 FB
10 EAP
9 DAC
8 EN
1234567
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP6213-DS-F0000
1
1 page  
uP6213
Functional Pin Description
Pin No.
VQFN6x6 VQFN4x4
Name Pin Function
21
15
IMAX
Output Current Indication. Connect a resistor from this pin to GND to set the
over current protection level.
22
16
OFS
Zero Current Offset. Connect a resistor form this pin to 5VCC or GND to set
the output offset voltage.
23
17
PS1
Power Saving Mode Setting Input 1. Connect a resistor from this pin to ground
to set the phase reduction threshold level.
24 NA ISEN4 Current Sensing for Phase4.
25 NA ISEN3 Current Sensing for Phase 3.
26 18 ISEN2 Current Sensing for Phase 2.
27 19 ISEN1 Current Sensing for Phase 1.
28
20
RT
Switching Frequency Programming. Connect a resistor from this pin to GND
to set the switching frequency.
29
21
5VCC
5V Supply Input. This pin receives a 5V voltage source to power the control
circuit. Connect this pin to ATX 5VCC.
30
23
TB
Transient Boost. This pin along with the VOUT pin set the transient boost
behavior.
31
22
VOUT
Output Voltage Sensing. This pin along with the TB pin set the transient boost
behavior.
32 NA TM Thermal Monitoring. Connect NTC network to this pin for thermal monitoring.
33 NA VR_HOT VR HOT Output.
34
NA
PWM4
PWM Output of Phase 4. Connect this pin to input pin of the companion gate
driver, such as uP6281.
35
NA
PWM3
PWM Output of Phase 3. Connect this pin to input pin of the companion gate
driver, such as uP6281.
36
24
PWM2
PWM Output of Phase 2. Connect this pin to input pin of the companion gate
driver, such as uP6281.
37
25
PWM1
PWM Output of Phase 1. Connect this pin to input pin of the companion gate
driver, such as uP6281.
38 NA NC Not Internally Connected.
39
NA
PS3
Power Saving Mode Setting Input 3. Connect a resistor from this pin to GND
to set the phase reduction threshold level.
40 NA VID7 Bit 7 of DAC Input. This pin is internally pulled high for uP6213B.
Exposed Pad
GND
Ground. Tie this pin to the ground island/plane through the lowest impedance
connection available.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP6213-DS-F0000
5
5 Page 
uP6213
Table 1. VRD10 + VID6 VID Table (Cont.) (VRSEL =
GND)
VID4 VID3 VID2
000
000
000
000
000
000
000
000
000
000
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
00 1
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
VID1 VID0 VID5 VID6
0 111
0 1 10
10 0 1
10 0 0
10 1 1
10
10
1 10 1
1 10 0
1111
1 1 10
000 1
0000
00 11
0 0 10
0 10 1
0 10 0
0 111
0 1 10
10 0 1
10 0 0
10 1 1
10
10
1 10 1
1 10 0
1111
1 1 10
000 1
0000
00 11
0 0 10
0 10 1
0 10 0
0 111
0 1 10
10 0 1
10 0 0
Voltage
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.89750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
Functional Description
L
DCR
VOUT
RCSP
RCSP
L
DCR
L
DCR
RCSP
CSP
CCS
CSN
RCSN
uP6213
GM
Amplifer
IAVG
Figure 2. Output Current Sensing of uP6213A/B.
Voltage Control Loop
Figure 3 illustrates the voltage control loop of the uP6213A/
B. FB and EAP are negative and positive inputs of the Error
Amplifier respectively. The Error Amplifier modulates the
COMP voltage VCOMP and the duty cycle of buck converter
to force FB voltage VFB follows VEAP.
As shown in Figure 3, VDAC is output of the internal VID
table. The slew rate of VDAC is limited by the capacitor
connected to SS pin during soft start and VID on the fly
transition. The sensed current signal is mirrored to the EAP
pin and creates voltage at EAP pin as:
VEAP = VDAC - RDRP x IAVG
where VDAC is a slew rate limited voltage source, IAVG is a
current source proportional to output current, and RDRP is
an external resistor for adjusting load line slope.
On the other hand, the inverting input voltage VFB can be
written as:
VFB = VOUT - RFB x IOFS
where VOUT is the output voltage, IOFS is a current source
for initial offset adjustment, ROFS is an external resistor.
Therefore, the output voltage will be:
VOUT = VDAC - RDRP x IAVG + RFB x IOFS
VOUT
=
VDAC
− IOUT
× DCR × RDRP
P × RCSN
+ RFB
× IOFS
Please see the related section for details.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP6213-DS-F0000
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet uP6213.PDF ] | |
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