74ALVCH16245 Datasheet PDF - ON Semiconductor
Part Number | 74ALVCH16245 | |
Description | Low-Voltage 16-Bit Transceiver | |
Manufacturers | ON Semiconductor | |
Logo | ||
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Low−Voltage 16−Bit
Transceiver with Bus Hold
1.8/2.5/3.3 V
(3−State, Non−Inverting)
The 74ALVCH16245 is an advanced performance, non−inverting
16−bit transceiver. It is designed for very high−speed, very low−power
operation in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16245 is designed with byte control. It can be
operated as two separate octals, or with the controls tied together, as a
16−bit wide function. The Transmit/Receive (T/Rn) inputs determine
the direction of data flow through the bi−directional transceiver.
Transmit (active−HIGH) enables data from A ports to B ports; Receive
(active−LOW) enables data from B to A ports. The Output Enable
inputs (OEn), when HIGH, disable both A and B ports by placing them
in a HIGH Z condition. The data inputs include active bushold
circuitry, eliminating the need for external pull−up resistors to hold
unused or floating inputs at a valid logic state.
• Designed for Low Voltage Operation: VCC = 1.65 − 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V†
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16245
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
74ALVCH16245DT
AWLYYWW
1
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
74ALVCH16245DTR TSSOP 2500/Tape & Reel
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to VCC through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 2
1
Publication Order Number:
74ALVCH16245/D
|
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74ALVCH16245
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits
Symbol
Parameter
Waveform
VCC = 3.0 V to 3.6 V
Min Max
TA = −40°C to +85°C
VCC = 2.3 V to 2.7 V VCC = 1.65 V to1.95 V
Min Max
Min
Max
Unit
tPLH Propagation Delay
tPHL Input to Output
1
1.0 3.0 1.0 3.7
1.0
6.0 ns
1.0 3.0 1.0 3.7
1.0
6.0
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
2
2
1.0 4.4 1.0 5.7
1.0 4.4 1.0 5.7
1.0 4.1 1.0 5.2
1.0 4.1 1.0 5.2
1.0
1.0
1.0
1.0
9.3 ns
9.3
7.6 ns
7.6
tOSHL
tOSLH
Output−to−Output Skew
(Note 11)
0.5 0.5
0.5 0.5
0.75 ns
0.75
10. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
CPD Power Dissipation Capacitance
12. VCC = 1.8, 2.5 or 3.3 V; VI = 0 V or VCC.
Condition
Note 12
Note 12
Note 12, 10MHz
An, Bn
Bn, An
Vm
tPLH
Vm
Vm
tPHL
Vm
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
OEn, T/Rn
An, Bn
An, Bn
Vm
tPZH tPHZ
Vm
Vm
tPZL tPLZ
Vm
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
Typical
6
7
20
VIH
0V
VOH
VOL
VIH
0V
VOH
Vy
≈0V
≈ VCC
Vx
VOL
Unit
pF
pF
pF
http://onsemi.com
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