HCPL-0720 Datasheet PDF - Avago
Part Number | HCPL-0720 | |
Description | CMOS Optocoupler | |
Manufacturers | Avago | |
Logo | ||
There is a preview and HCPL-0720 download ( pdf file ) link at the bottom of this page. Total 19 Pages |
Preview 1 page No Preview Available ! HCPL-0720/7720/0721/7721
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RcoomHSpl6iafnutlly
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-772X or HCPL-072X optocouplers
utilize the latest CMOS IC technology to achieve out-
standing performance with very low power consump-
tion. The HCPL-772X/072X require only two bypass ca-
pacitors for complete CMOS compatability.
Basic building blocks of the HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver IC
which supplies current to the LED. The detector IC incor-
porates an integrated photodiode, a high-speed tran-
simpedance amplifier, and a voltage comparator with an
output driver.
Functional Diagram
• +5 V CMOS compatibility
• 20 ns maximum prop. delay skew
• High speed: 25 MBd
• 40 ns max. prop. delay
• 10 kV/µs minimum common mode rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals
UL recognized
– 3750 Vrms for 1 min. per UL 1577
– 5000 Vrms for 1 min. per UL 1577
(for HCPL-772X option 020)
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-2
– VIORM = 630 Vpeak for HCPL-772X option 060
– VIORM = 560 Vpeak for HCPL-072X option 060
**VDD1 1
VI 2
*3
GND1 4
LED1
SHIELD
8 VDD2**
7 NC*
IO
6 VO
5 GND2
(PTORSUITTIHVAETpALpOBlLGicEIaCt)ions
VI, INPUT
H
L
LED•1 DiVgOit,aOlUfiTePlUdTbus isolation: CC-Link, DeviceNet, Profi-
OFF bus, SDHS
ON
•
AC
plasLma
display
panel
level
shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left unconnected
for guaranteed data sheet performance. Pin 7 is not connected
internally.
** A 0.1 µF bypass capacitor must be connected between pins 1 and
4, and 5 and 8.
TRUTH TABLE
POSITIVE LOGIC
VI LED1 Vo OUTPUT
H OFF H
L ON L
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
|
|
Solder Reflow Thermal Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
TEMP.
245°C
200
160°C
150°C
140°C
100
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
PREHEATING TIME
150°C, 90 + 30 SEC.
30
SEC.
30
SEC.
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
SOLDERING
TIME
200°C
50 SEC.
ROOM
TEMPERATURE
00
TIGHT
TYPICAL
LOOSE
50 100 150 200 250
TIME (SECONDS)
Note: Non-halide flux should be used.
Pb-Free IR Profile
Tp
TL
217 °C
260 +0/-5 °C
RAMP-UP
3 °C/SEC. MAX.
Tsmax 150 - 200 °C
Tsmin
ts
PREHEAT
60 to 180 SEC.
tp
tL
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
RAMP-DOWN
6 °C/SEC. MAX.
60 to 150 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-772X/072X have been approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01. (Option 060 only)
Preview 5 Page |
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Information | Total 19 Pages | |
Link URL | [ Copy URL to Clipboard ] | |
Download | [ HCPL-0720.PDF Datasheet ] |
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