UPD424210 Datasheet PDF - NEC
Part Number | UPD424210 | |
Description | 4 M-BIT DYNAMIC RAM | |
Manufacturers | NEC | |
Logo | ||
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MOS INTEGRATED CIRCUIT
µPD424210
4 M-BIT DYNAMIC RAM
256K-WORD BY 16-BIT, EDO,
BYTE READ/WRITE MODE
Description
The µPD424210 is a 262,144 words by 16 bits CMOS dynamic RAM with optional EDO.
EDO is a kind of page mode and is useful for the read operation.
The µPD424210 is packaged in 44-pin plastic TSOP (II) and 40-pin plastic SOJ.
Features
• EDO (Hyper page mode)
• 262,144 words by 16 bits organization
• Single power supply
+5.0 V ± 10 % : µPD424210-60, 424210-70
+5.0 V ± 5 % : µPD424210-60-G
Part number
µPD424210-60
µPD424210-60-G
µPD424210-70
Power consumption
Active (MAX.)
880 mW
840 mW
825 mW
Access time
(MAX.)
60 ns
60 ns
70 ns
R/W cycle time
(MIN.)
104 ns
104 ns
124 ns
EDO (Hyper page mode)
cycle time (MIN.)
25 ns
25 ns
30 ns
Part number
µPD424210-60
µPD424210-70
µPD424210-60-G
Refresh cycle
512 cycles/8 ms
512 cycles/8 ms
Refresh
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
Power consumption at standby
(MAX.)
5.5 mW
(CMOS level input)
5.25 mW
(CMOS level input)
The information in this document is subject to change without notice.
Document No. M12941EJ1V0DS00 (1st edition)
Date Published September 1997 N
Printed in Japan
©
1997
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µPD424210
Input/Output Pin Functions
The µPD424210 has input pins RAS, CASNote, WE, OE, A0 to A8 and input/output pins I/O1 to
I/O16.
Pin name
Input/Output
Function
RAS
(Row address strobe)
CAS
(Column address strobe)
A0 to A8
(Address inputs)
WE
(Write enable)
OE
(Output enable)
I/O1 to I/O16
(Data inputs/outputs)
Input
Input
Input
Input
Input
Input/Output
RAS activates the sense amplifier by latching a row address and selecting a
corresponding word line.
It refreshes memory cell array of one line selected by the row address.
It also selects the following function.
• CAS before RAS refresh
CAS activates data input/output circuit by latching column address and
selecting a digit line connected with the sense amplifier.
Address bus.
Input total 18-bit of address signal, upper 9-bit and lower 9-bit in sequence
(address multiplex method).
Therefore, one word is selected from 262,144-word by 16-bit memory cell
array.
In actual operation, latch row address by specifying row address and
activating RAS.
Then, switch the address bus to column address and activate CAS.
Each address is taken into the device when RAS and CAS are activated.
Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH)
are specified for the activation of RAS and CAS.
Write control signal.
Write operation is executed by activating RAS, CAS and WE.
Read control signal.
Read operation can be executed by activating RAS, CAS and OE.
If WE is activated during read operation, OE is to be ineffective in the device.
Therefore, read operation cannot be executed.
16-bit data bus.
I/O1 to I/O16 are used to input/output data.
Note CAS means UCAS and LCAS.
5
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