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What is GAL26CLV12D-7LJ?

This electronic component, produced by the manufacturer "Lattice Semiconductor", performs the same function as "Low Voltage E2CMOS PLD Generic Array Logic".


GAL26CLV12D-7LJ Datasheet PDF - Lattice Semiconductor

Part Number GAL26CLV12D-7LJ
Description Low Voltage E2CMOS PLD Generic Array Logic
Manufacturers Lattice Semiconductor 
Logo Lattice Semiconductor Logo 


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Total 13 Pages



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GAL26CLV12
Low Voltage E2CMOS PLD
Generic Array Logic™
FFEeAaTtUuRrEeSs
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 200 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— Inputs and I/O Interface with Standard 5V TTL Devices
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
I
I
I
I
I
RESET
8
OLMC
8
OLMC
8
OLMC
8
OLMC
10
OLMC
12
OLMC
12
OLMC
10
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
PRESET
INPUT
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Description
The GAL26CLV12D, at 5 ns maximum propagation delay time,
provides higher performance than its 5V counterpart. The
GAL26CLV12D can interface with both 3.3V and 5V signal levels.
The GAL26CLV12D is manufactured using Lattice Semiconductor's
advanced 3.3V E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology. High speed erase
times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4 2 28 26
I
I
VCC
I
I
I
I
5 25
7 GAL26CLV12D 23
Top View
9 21
11 19
12 14 16 18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
26clv12_02
1

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GAL26CLV12D-7LJ equivalent
Specifications GAL26CLV12
GAL26CLV12D Logic Diagram/JEDEC Fuse Map
PLCC Package Pinout
1
0 4 8 12 16 20 24 28 32 36 40 44 48
0000
0052
.
.
.
0468
2
0520
.
.
.
0936
3
0988
.
.
.
1404
4
1456
.
.
.
1872
5
1924
.
.
.
.
2444
6
2496
.
.
.
.
.
3120
8
3172
.
.
.
.
.
3796
9
3848
.
.
.
.
4368
10
4420
.
.
.
4836
11
4888
.
.
.
5304
12
5356
.
.
.
5772
13
5824
.
.
.
6240
14
6292
6368, 6369 ... Electronic Signature ... 6430, 6431
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
ML
SS
BB
28
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
8 OLMC
S0
6344
S1
6345
27
8 OLMC
S0
6346
S1
6347
26
8 OLMC
S0
6348
S1
6349
25
8 OLMC
S0
6350
S1
6351
24
10 OLMC
S0
6352
S1
6353
23
12
OLMC
S0
6354
S1
6355
22
12
OLMC
S0
6356
S1
6357
20
10 OLMC
S0
6358
S1
6359
19
8 OLMC
S0
6360
S1
6361
18
8 OLMC
S0
6362
S1
6363
17
8 OLMC
S0
6364
S1
6365
16
8 OLMC
S0
6366
S1
6367
15
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
5


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Part Details

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Featured Datasheets

Part NumberDescriptionMFRS
GAL26CLV12D-7LJThe function is Low Voltage E2CMOS PLD Generic Array Logic. Lattice SemiconductorLattice Semiconductor

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