PDF GAL16V8ZD-15QJ Data sheet ( Hoja de datos )

Número de pieza	GAL16V8ZD-15QJ
Descripción	Zero Power E2CMOS PLD
Fabricantes	Lattice Semiconductor
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GAL16V8Z GAL16V8ZD Zero Power E2CMOS PLD Features • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 12 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 8 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Output Drive — UltraMOS® Advanced CMOS Technology • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity — Architecturally Similar to Standard GAL16V8 • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability • APPLICATIONS INCLUDE: — Battery Powered Systems — DMA Control — State Machine Control — High Speed Graphics Processing • ELECTRONIC SIGNATURE FOR IDENTIFICATION Functional Block Diagram I/CLK CLK I I I/DPP I I I I I 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC OE I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/OE Description The GAL16V8Z and GAL16V8ZD, at 100 µA standby current and 1D2EnSs CpRroIpPaTgIOatNion delay provides the highest speed and lowest power combination PLD available in the market. The GAL16V8Z/ ZD is manufactured using Lattice Semiconductor's advanced zero power E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. The GAL16V8Z uses Input Transition Detection (ITD) to put the device in standby mode and is capable of emulating the full func- tionality of the standard GAL16V8. The GAL16V8ZD utilizes a dedicated power-down pin (DPP) to put the device in standby mode. It has 15 inputs available to the AND array. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Pin Configuration DIP/SOIC PLCC 3 1 19 I/DPP 4 1 8 I/O/Q GAL16V8Z I I/O/Q GAL16V8ZD I6 1 6 I/O/Q Top View I I/O/Q I 89 1 1 1 31 4 I/O/Q I/CLK I I I/DPP I I I I I GND 1 20 2 19 3 GAL 18 4 16V8Z 17 5 16V8ZD 16 6 15 7 14 8 13 9 12 10 11 Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/OE Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com December 1997 16v8zzd_03 1 1 page Specifications GAL16V8Z GAL16V8ZD Registered Mode Logic Diagram DIP, SOIC & PLCC Package Pinouts 1 2128 0 4 8 12 16 20 24 28 PTD 0000 OLMC 0224 2 XOR-2048 AC1-2120 0256 0480 3 OLMC XOR-2049 AC1-2121 4 0512 0736 OLMC XOR-2050 AC1-2122 0768 0992 5 OLMC XOR-2051 AC1-2123 1024 1248 6 OLMC XOR-2052 AC1-2124 1280 1504 7 OLMC XOR-2053 AC1-2125 1536 1760 8 OLMC XOR-2054 AC1-2126 1792 2016 9 OLMC XOR-2055 AC1-2127 2191 19 18 17 16 15 14 13 12 OE 11 MSB 64-USER ELECTRONIC SIGNATURE FUSES 2056, 2057, .... .... 2118, 2119 Byte7 Byte6 .... .... Byte1 Byte0 LSB SYN-2192 AC0-2193 Note: Input not available on GAL16V8ZD 5 5 Page Specifications GAL16V8Z SpecificationGs GALA1L61V68VZ8DZ AC Switching Characteristics Over Recommended Operating Conditions TEST PARAMETER COND1. DESCRIPTION tpd A Input or I/O to Combinational Output tco A Clock to Output Delay tcf2 — Clock to Feedback Delay tsu — Setup Time, Input or Feedback before Clock↑ th — Hold Time, Input or Feedback after Clock↑ A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) fmax3 A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with No Feedback twh — Clock Pulse Duration, High twl — Clock Pulse Duration, Low ten B Input or I/O to Output Enabled B OE to Output Enabled tdis C Input or I/O to Output Disabled C OE to Output DIsabled tas — Last Active Input to Standby tsa4 — Standby to Active Output COM -12 MIN. MAX. 3 12 COM -15 UNITS MIN. MAX. 3 15 ns 2 8 2 10 ns —6—7 ns 10 — 15 — ns 0 — 0 — ns 55 — 40 — MHz 62.5 — 45.5 — MHz 83.3 — 62.5 — MHz 6—8— 6—8— — 12 — 15 — 12 — 15 — 15 — 15 — 12 — 15 60 140 50 150 6 13 5 15 ns ns ns ns ns ns ns ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. 4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state. Standby Power Timing Waveforms POWER Icc Isb INPUT or I/O FEEDBACK tas OE CLK OUTPUT tsa tpd ten, tdis * tsu tco * Note: Rising clock edges are allowed during tsa but outputs are not guaranteed. 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
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