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PDF 74ACT14 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT14 | |
| Descripción | Hex Inverter | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74ACT14 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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74AC14 • 74ACT14
Hex Inverter with Schmitt Trigger Input
November 1988
Revised September 2005
General Description
The 74AC14 and 74ACT14 contain six inverter gates each with
a Schmitt trigger input. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free output sig-
nals. In addition, they have a greater noise margin than conven-
tional inverters.
The 74AC14 and 74ACT14 have hysteresis between the posi-
tive-going and negative-going input thresholds (typically 1.0V)
which is determined internally by transistor ratios and is essen-
tially insensitive to temperature and supply voltage variations.
Features
O ICC reduced by 50%
O Outputs source/sink 24 mA
O 74ACT14 has TTL-compatible inputs
Ordering Code:
Order Number
74AC14SC
74AC14SCX_NL
(Note 1)
74AC14SJ
74AC14MTC
74AC14MTCX_NL
(Note 1)
74AC14PC
74ACT14SC
74ACT14MTC
74ACT14MTCX_NL
(Note 1)
74ACT14PC
Package
Number
M14A
M14A
M14D
MTC14
MTC14
N14A
M14A
MTC14
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009917
www.fairchildsemi.com
1 page  
AC Electrical Characteristics for ACT
Symbol
Parameter
tPLH Propagation Delay
Data to Output
tPHL Propagation Delay
Data to Output
Note 9: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
VCC
(V)
(Note 9)
5.0
5.0
TA 25qC
CL 50 pF
Min Typ Max
3.0 8.0 10.0
3.0 8.0 10.0
TA 40qC to 85qC
CL 50 pF
Min Max
3.0 11.0
3.0 11.0
Units
ns
ns
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance for AC
for ACT
Typ
4.5
25.0
80
Units
pF
pF
VCC OPEN
VCC 5.0V
Conditions
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74ACT14.PDF ] | |
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