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PDF ITC117PLTR Data sheet ( Hoja de datos )
| Número de pieza | ITC117PLTR | |
| Descripción | 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential
LVPECL Clock Multiplexer
Features
ÎÎPin-to-pin compatible to ICS85352I
ÎÎFMAX ≤ 500 MHz
ÎÎPropagation Delay < 4ns
ÎÎOutput-to-output skew < 100ps
ÎÎ12 pairs of differential LVPECL outputs
ÎÎSelectable differential CLK and /CLK inputs
ÎÎCLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and
HCSL input level
ÎÎSelect input accept CMOS/LVTTL levels
ÎÎ2.5V/3.3V power supply
ÎÎOperating Temperature: -40°C to +85°C
ÎÎPackaging (Pb-free & Green):
— 48-pin TQFP (FA)
Description
The PI6C485352 is a high-performance low-skew LVPECL
fanout buffer. PI6C485352 features two selectable differential
inputs and translates to twelve LVPECL output pairs. The inputs
can also be configured to single-ended with external resistor
bias circuit. The CLK input accepts LVPECL, LVDS, LVHSTL,
SSTL or HCSL signals. The PI6C485352 is ideal for differential
to LVPECL translations and/or LVPECL clock distribution.
Typical clock translation and distribution applications are data-
communications and telecommunications.
Applications
ÎÎNetworking systems including switches and Routers
ÎÎHigh frequency backplane based computing and telecom
platforms
Block Diagram
Pin Configuration (48-Pin TQFP)
SEL [0:11]
CLK0
/CLK0
CLK1
/CLK1
12
0
1
0
1
48 47 46 45 44 43 42 41 40 39 38 37
Q0 1
36 Q6
/Q0 2
35 /Q6
Q1 3
34 Q7
/Q1 4
33 /Q7
Q0 Q2 5
/Q0 /Q2 6
32 Q8
31 /Q8
Q3 7
30 Q9
/Q3 8
29 /Q9
Q4 9
28 Q10
/Q4 10
27 /Q10
Q11 Q5 11
26 Q11
/Q11 /Q5 12
25 /Q11
13 14 15 16 17 18 19 20 21 22 23 24
13-0003
1
PI6C485352 Rev. A
01/24/13
1 page  
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
AC Characteristics (TA = -40°C to +85°C, VCC = 3.3V ±10%, VCCO = 2.5V ±5% to 3.3V ±10%)
Parameter Description
Conditions
Min.
Typ. Max. Units
fmax
Output Frequency
500 MHz
tpd Propagation Delay(1)
4 ns
Tsk Output-to-output Skew(2)
100 ps
Tskpp
Part-to-part Skew(3)
500 ps
tr/tf Output Rise/Fall time
20% - 80%
150
700 ps
odc Output duty cycle
45 55 %
Tj Buffer additive jitter RMS
0.05 ps
Note:
1.Measured from the differential input to the differential output crossing point
2 Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing
point.
3. Defined as skew between outputs on different parts operating at the same supply voltage and with equal loads. Measured at the
outputs differential crossing point.
13-0003
5
PI6C485352 Rev. A
01/24/13
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ITC117PLTR.PDF ] | |
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