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PDF UC2843A Data sheet ( Hoja de datos )
| Número de pieza | UC2843A | |
| Descripción | High Performance Current Mode Controllers | |
| Fabricantes | ON Semiconductor | |
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 1. High Performance Current Mode Controllers  Hay una vista previa y un enlace de descarga de UC2843A (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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UC3842A, UC3843A,
UC2842A, UC2843A
High Performance
Current Mode Controllers
The UC3842A, UC3843A series of high performance fixed
frequency current mode controllers are specifically designed for
off−line and DC−to−DC converter applications offering the designer a
cost effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in an 8−pin dual−in−line plastic package
as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14
package has separate power and ground pins for the totem pole output
stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX843A is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
• Trimmed Oscillator Discharge Current for Precise Duty Cycle
Control
• Current Mode Operation to 500 kHz
• Automatic Feed Forward Compensation
• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with ON Semiconductor SENSEFET™ Products
• Pb−Free Packages are Available
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8
1
14
1
PDIP−8
N SUFFIX
CASE 626
SOIC−14
D SUFFIX
CASE 751A
8
1
SOIC−8
D1 SUFFIX
CASE 751
PIN CONNECTIONS
Compensation 1
Voltage Feedback 2
Current Sense 3
RT/CT 4
8 Vref
7 VCC
6 Output
5 GND
(Top View)
Compensation 1
NC 2
Voltage Feedback 3
NC 4
Current Sense 5
NC 6
RT/CT 7
14 Vref
13 NC
12 VCC
11 VC
10 Output
9 GND
8 Power Ground
(Top View)
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 8
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 16 of this data sheet.
1 Publication Order Number:
UC3842A/D
1 page  
UC3842A, UC3843A, UC2842A, UC2843A
80
50
20
8.0
5.0
2.0 VCC = 15 V
TA = 25°C
0.8
10 k
20 k
50 k 100 k 200 k
500 k
fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 2. Timing Resistor versus
Oscillator Frequency
1.0 M
100
50
VCC = 15 V
TA = 25°C
20
10
5.0
2.0
1.0
10 k
20 k
50 k 100 k 200 k
500 k
fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 3. Output Deadtime versus
Oscillator Frequency
1.0 M
9.0
VCC = 15 V
VOSC = 2.0 V
8.5
8.0
7.5
7.0
−55
−25 0 25 50 75 100
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Oscillator Discharge Current
versus Temperature
125
100
VCC = 15 V
90
CT = 3.3 nF
TA = 25°C
80 Idischg = 7.2 mA
70
60
50 Idischg = 9.5 mA
40
800 1.0 k
2.0 k 3.0 k 4.0 k 6.0 k 8.0 k
RT, TIMING RESISTOR (W)
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
2.55 V
2.5 V
VCC = 15 V
AV = −1.0
TA = 25°C
3.0 V
2.5 V
VCC = 15 V
AV = −1.0
TA = 25°C
2.45 V
0.5 ms/DIV
Figure 6. Error Amp Small Signal
Transient Response
2.0 V
0.1 ms/DIV
Figure 7. Error Amp Large Signal
Transient Response
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5
5 Page 
UC3842A, UC3843A, UC2842A, UC2843A
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High Frequency
circuit layout techniques are imperative to prevent pulse
width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 mF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed−loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t0, switch
conduction begins, causing the inductor current to rise at a
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m2 until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small DI (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t2) is increased
by DI + DI m2/m1. The minimum current at the next cycle
(t3) decreases to (DI + DI m2/m1) (m2/m1). This perturbation
is multiplied by m2.m1 on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m2/m1 is greater than 1, the converter
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the DI perturbation will decrease to zero
on succeeding cycles. This compensation ramp (m3) must
have a slope equal to or slightly greater than m2/2 for
stability. With m2/2 slope compensation, the average
inductor current follows the control voltage yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
DI
Control Voltage
Inductor
Current
m2
m1 DI + DI m2
m1
Oscillator Period
t0 t1
(A)
D
I
+
DI
m2
m1
t2
m2
m1
t3
Control Voltage
(B)
m3
DI
m1
m2 Inductor
Current
Oscillator Period
t4 t5
t6
Figure 20. Continuous Current Waveforms
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11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet UC2843A.PDF ] | |
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