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PDF GDC21D301A Data sheet ( Hoja de datos )
| Número de pieza | GDC21D301A | |
| Descripción | Transport Decoder | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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GDC21D301A
(Transport Decoder)
Version 1.5
HDS-GDC21D301A-9908 / 10
1 page  
3. Pin Description
GDC21D301A
DSP_DATA[13]
DSP_DATA[14]
DSP_DATA[15]
VSS
DSP_INT
DSP_READY
VDD
TDO0
TDO1
VDD
HSDEN
HIGH_SP_DATA[1]
HIGH_SP_DATA[0]
CLOCK_OUT
VSS
TA[7]
TA[6]
TA[5]
TA[4]
TA[3]
TA[2]
TA[1]
TA[0]
VSS
TWEB
TEST
TDI
P_S_MODE
F_START
FEC_DATA[7]
FEC_DATA[6]
FEC_CLOCK
VDD
NC
VSS
FEC_DATA[5]
FEC_DATA[4]
FEC_DATA[3]
FEC_DATA[2]
FEC_DATA[1]
FEC_DATA[0]
ERR_BLOCK_B
D_VALID
S C A N _ M O D E /T A [ 8 ]
176
1
45
HME
GDC21D301A
YYWW
133
89
NC
NC
VSS
\DSP_PD
DSP_RWB
\DSP_STRB
VPW M
\VID_STRB
VDD
\VID_DCS
VAD_DATA[0]
VDD
VAD_DATA[1]
VAD_DATA[2]
VSS
VAD_DATA[3]
VAD_DATA[4]
VAD_DATA[5]
VAD_DATA[6]
VDD
\RESET
SCAN_OUT1
VAD_DATA[7]
PTS_DTS_STRB
\DATA_STRB
\DATA_DCS
VSS
\AUD_STRB
AUD_SER_DATA
\AUD_DCS
VSS
APW M
VDD
BOF_V
BOF_A
BOF_D
\VID_REQ
\VID_W AIT
\AUD_REQ
\AUD_W AIT
\DATA_REQ
\DATA_W AIT
DRAM_DATA[0]
DRAM_DATA[1]
Figure 1. Pin Description
6
5 Page 
4. Block Diagram
The figure 2 shows the internal block diagram of
the GDC21D301A. This chip receives the byte-
parallel/bit-serial transport data from
FEC(Forward-Error-Correction) device, and stores
the whole data into DRAM. After decoding the
transport data in DRAM, it de-multiplexes audio,
video, and auxiliary data packets, and transfers
them into the corresponding decoder devices
GDC21D301A
through the decoder interface blocks. The host
processor can control the GDC21D301A and
access the decoder devices and DRAM through the
host interface. The GDC21D301A generates PWM
pulses to control the frequency of system clock and
audio clock. The pulse width of PWM can be
programmed by the host processor.
FEC
Decoder
Transport
Stream
FEC
Interface
88/1/166bbitit
MMCCUU
Host
Interface
PID
Memory
TS Buffer
Sync
Detect
Buffer
TS Header
Decode
VCXO
Clock
Control
Adaptation
Field
Decode
PES
Decode
Memory
Controller
4Mb
DRAM
High-speed
Interface
External
Decoder
Interface
Figure 2. The Block Diagram of the Transport Decoder
12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GDC21D301A.PDF ] | |
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