GD82559ER Datasheet PDF - Intel Corporation
Part Number | GD82559ER | |
Description | PCI Controller | |
Manufacturers | Intel Corporation | |
Logo | ||
There is a preview and GD82559ER download ( pdf file ) link at the bottom of this page. Total 70 Pages |
Preview 1 page No Preview Available ! GD82559ER Fast Ethernet**
PCI Controller
Networking Silicon
Product Features
Datasheet
s Optimum Integration for Lowest Cost
Solution
— Integrated IEEE 802.3 10BASE-T and
100BASE-TX compatible PHY
— Glueless 32-bit PCI master interface
— 128 Kbyte Flash interface
— Thin BGA 15mm2 package
— ACPI and PCI Power Management
— Power management event on
“interesting” packets and link status
change support
— Test Access Port
s High Performance Networking Functions
— Chained memory structure similar to the
82559,82558, 82557, and 82596
— Improved dynamic transmit chaining
with multiple priorities transmit queues
— Full Duplex support at both 10 and 100
Mbps
— IEEE 802.3u Auto-Negotiation support
— 3 Kbyte transmit and 3 Kbyte receive
FIFOs
— Fast back-to-back transmission support
with minimum interframe spacing
— IEEE 802.3x 100BASE-TX Flow
Control support
— Low Power Features
— Low power 3.3 V device
— Efficient dynamic standby mode
— Deep power down support
— Clockrun protocol support
Document Number: 714682-001
Revision 1.0
March 1999
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Networking Silicon — GD82559ER
8.1.10 Flow Control Register .......................................................................................60
8.1.11 Power Management Driver Register ................................................................60
8.1.12 General Control Register..................................................................................61
8.1.13 General Status Register ...................................................................................61
8.2 Statistical Counters...........................................................................................................62
9. PHY UNIT REGISTERS ................................................................................................................65
9.1 MDI Registers 0 - 7...........................................................................................................65
9.1.1 Register 0: Control Register Bit Definitions .....................................................65
9.1.2 Register 1: Status Register Bit Definitions .......................................................66
9.1.3 Register 2: PHY Identifier Register Bit Definitions ...........................................67
9.1.4 Register 3: PHY Identifier Register Bit Definitions ...........................................67
9.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions ..............67
9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions .......67
9.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions ....................68
9.2 MDI Registers 8 - 15.........................................................................................................68
9.3 MDI Register 16 - 31 ........................................................................................................ 68
9.3.1 Register 16: PHY Unit Status and Control Register Bit Definitions .................68
9.3.2 Register 17: PHY Unit Special Control Bit Definitions .....................................69
9.3.3 Register 18: PHY Address Register .................................................................70
9.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions ......70
9.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions .........70
9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions ........70
9.3.7 Register 22: Receive Symbol Error Counter Bit Definitions ............................70
9.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter
Bit Definitions ..................................................................................................71
9.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions .71
9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions ........71
9.3.11 Register 26: Equalizer Control and Status Bit Definitions ................................71
9.3.12 Register 27: PHY Unit Special Control Bit Definitions .....................................71
10. ELECTRICAL AND TIMING SPECIFICATIONS ..........................................................................73
10.1 Absolute Maximum Ratings ..............................................................................................73
10.2 DC Specifications ............................................................................................................73
10.3 AC Specifications .............................................................................................................76
10.4 Timing Specifications........................................................................................................77
10.4.1 Clocks Specifications .......................................................................................77
10.4.2 Timing Parameters ...........................................................................................78
12. PACKAGE AND PINOUT INFORMATION ...................................................................................85
12.1 Package Information.........................................................................................................85
12.2 Pinout Information ............................................................................................................86
12.2.1 GD82559ER Pin Assignments ........................................................................86
12.2.2 GD82559ER Ball Grid Array Diagram .............................................................88
Datasheet
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