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What is GS70328SJ-15?

This electronic component, produced by the manufacturer "ETC", performs the same function as "32K x 8 256Kb Asynchronous SRAM".


GS70328SJ-15 Datasheet PDF - ETC

Part Number GS70328SJ-15
Description 32K x 8 256Kb Asynchronous SRAM
Manufacturers ETC 
Logo ETC Logo 


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SOJ, TSOP
Commercial Temp
Industrial Temp
32K x 8
256Kb Asynchronous SRAM
GS70328SJ/TS
7, 8, 10, 12, 15 ns
3.3 V VDD
Corner VDD and VSS
Features
• Fast access time: 7, 8, 10, 12, 15 ns
• 75/65/50/50/50 mA at max cycle rate
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
SJ: 300 mil, 28-pin SOJ package
TS: 8 mm x 13.4 mm, 28-pin TSOP Type I package
Pin Descriptions
Symbol
A0–A14
DQ1–DQ8
CE
WE
Description
The GS70328 is a high speed CMOS static RAM organized as
32,763 words by 8 bits. Static design eliminates the need for
external clocks or timing strobes. The GS70328 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS70328 is available in 300 mil, 28-pin SOJ
and 8 x 13.4 mm2, 28-pin TSOP Type-I packages.
OE
VDD
VSS
NC
Pin Configuration
Top view
A14 1
A12 2
28 VDD
27 WE
A7 3
26 A13
A6 4
25
A5 5
24
A4 6 28-pin 23
A3 7
22
300 mil
A2 8
21
A1 9 SOJ 20
A0 10
19
DQ1 11
18
DQ2 12
17
A8
A9
A11
OE
A10
CE
DQ8
DQ7
DQ6
OE 1
A11 2
A9 3
A8 4
A13 5
WE 6
VDD 7
A14 8
A12 9
A7 10
A6 11
A5 12
A4 13
A3 14
DQ3 13
16 DQ5
VSS 14
15 DQ4
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
28- pin
8 x 13.4 TSOP I
28 A10
27 CE
26 DQ8
25 DQ7
24 DQ6
23 DQ5
22 DQ4
21 VSS
20 DQ3
19 DQ2
18 DQ1
17 A0
16 A1
15 A2
Rev: 1.10 10/2002
1/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

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GS70328SJ-15 equivalent
GS70328SJ/TS
AC Characteristics
Read Cycle
Parameter
-7 -8 -10 -12 -15
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max
Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
tRC 7 — 8 — 10 — 12 — 15 — ns
tAA — 7 — 8 — 10 — 12 — 15 ns
tAC — 7 — 8 — 10 — 12 — 15 ns
tOE — 3.5 — 4 — 5 — 6 — 7 ns
tOH 2 — 2 — 2 — 3 — 3 — ns
Chip enable to output in low Z (CE)
tLZ* 2 — 2 — 2 — 3 — 3 — ns
Output enable to output in low Z (OE)
tOLZ* 0 — 0 — 0 — 0 — 0 — ns
Chip disable to output in High Z (CE)
tHZ* — 3.5 — 4 — 5 — 6 — 7 ns
Output disable to output in High Z (OE)
tOHZ*
3 — 3.5 —
4
5
6
ns
* These parameters are sampled and are not 100% tested
Rev: 1.10 10/2002
5/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for GS70328SJ-15 electronic component.


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