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PDF GTLP6C816 Data sheet ( Hoja de datos )
| Número de pieza | GTLP6C816 | |
| Descripción | GTLP-to-TTL 1:6 Clock Driver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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June 1998
Revised October 1998
GTLP6C816
GTLP-to-TTL 1:6 Clock Driver
General Description
The GTLP6C816 is a clock driver that provides TTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
TTL logic levels and a backplane operating at GTLP logic
levels. High speed backplane operation is a direct result of
GTLP’s reduced output swing (<1V), reduced input thresh-
old levels and output edge rate control. The edge rate con-
trol minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Interface between TTL and GTLP logic levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down high impedance for live insertion
s 1:6 fanout clock driver for TTL port
s 1:2 fanout clock driver for GTLP port
s TTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s Recommended Operating Temperature −40°C to +85°C
Ordering Code:
Order Number Package Number Package Description
GTLP6C816MTC MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Descriptions
Connection Diagram
Pin Names
Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW)
GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW)
TTL Port (TTL Levels)
VCCT.GNDT
VCC
GNDG
TTL Output Supplies (5V)
Internal Circuitry VCC (5V)
OBn GTLP Output Grounds
VREF
OA0–OA5
Voltage Reference Input
TTL Buffered Clock Outputs
OB0–OB1
GTLP Buffered Clock Outputs
© 1998 Fairchild Semiconductor Corporation DS500129.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature. VREF = 1.0V (unless otherwise noted).
CL = 30 pF for OBn-Port and CL = 50 pF for OAn-Port.
Symbol
From (Input)
To (Output)
Min
Typ
(Note 6)
Max
Units
tPLH
tPHL
tPLH
tPHL
tRISE
tFALL
tRISE
tFALL
tPZH, tPZL
tPLZ, tPHZ
tPLH
tPHL
tOSHL, tOSLH
(Note 7)
TTLIN
OBn
OEB
OBn
Transition Time, OB Outputs (20% to 80%)
Transition Time, OB outputs (20% to 80%)
Transition Time, OA outputs (10% to 90%)
Transition Time, OA outputs (10% to 90%)
OEA
OAn
GTLPIN
OAn
Common Edge Skew
1.5 3.8 6.0
ns
1.5 2.8 5.0
1.5 6.4 10.5
ns
1.5 3.2 6.0
2.3 ns
2.3 ns
2.0 ns
2.0 ns
0.5 3.6 6.5
ns
0.5 3.8 6.5
1.5 4.4 6.5
ns
1.5 4.0 6.0
0.2 1.0 ns
Note 6: All typical values are at VCC = 5.0V and TA = 25°C.
Note 7: Skew specs are given for specific worst case VCC Temp. Skew values between the OBn outputs could vary on the backplane due to loading and
impedance seen by the device.
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet GTLP6C816.PDF ] | |
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