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What is GS9000CCTJ?

This electronic component, produced by the manufacturer "ETC", performs the same function as "Serial Digital Decoder".


GS9000CCTJ Datasheet PDF - ETC

Part Number GS9000CCTJ
Description Serial Digital Decoder
Manufacturers ETC 
Logo ETC Logo 


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GENLINXGS9000C
Serial Digital Decoder
FEATURES
• fully compatible with SMPTE 259M
• decodes 8 and 10 bit serial digital signals for data
rates to 370Mb/s
• pin and function compatible with GS9000S, GS9000
and GS9000B
• 325mW power dissipation at 270MHz clock rates
• incorporates an automatic standards selection
function with the GS9005A Receiver or GS9015A
Reclocker
• operates from single +5 or -5 volt supply
• enables an adjustment-free Deserializer system
when used with GS9010A and GS9005A or
GS9015A
• 28 pin PLCC packaging
APPLICATIONS
• 4ƒSC, 4:2:2 and 360Mb/s serial digital interfaces
• Automatic standards select controller for serial routing
and distribution applications using GS9005A Receiver or
GS9015A Reclocker
DATA SHEET
DEVICE DESCRIPTION
The GS9000C is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates to 370Mb/s.
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC,
Sync Warning and Standard Select are all TTL compatible.
The GS9000C is designed to directly interface with the
GS9005A Reclocking Receiver to form a complete
SMPTE-serial-in to CMOS level parallel-out deserializer.
The GS9000C may also be used with the GS9010A and
the GS9005A to form an adjustment-free receiving system
which automatically adapts to all serial digital data rates.
The GS9015A can replace the GS9005A in GS9000C
applications where cable equalization is not required.
The GS9000C is packaged in a 28 pin PLCC and operates
from a single 5 volt, ± 5% power supply.
SERIAL DATA IN 5
SERIAL DATA IN 6
LEVEL
SHIFT
SERIAL CLOCK IN 7
8
SERIAL CLOCK IN
LEVEL
SHIFT
SYNC CORRECTION 14
ENABLE
SYNC WARNING 15
CONTROL
STANDARDS SELECT 11
CONTROL
GS9000C
DESCRAMBLER
30 - BIT
SHIFT REG
SP
SCLK
SYNC DETECT
(3FF 000 000 HEX)
Sync
Word
Boundary
PARALLEL
TIMING
GENERATOR
SYNC CORRECTION
Sync Error
SYNC WARNING
(Schmitt Trigger
Comparator)
AUTO STANDARD SELECT
OSC
2 BIT
COUNTER
Hsync Reset
PARALLEL DATA
OUT (10 BITS)
PARALLEL CLOCK
OUT
HSYNC OUTPUT
SYNC WARNING
FLAG
SS0
SS1
FUNCTIONAL BLOCK DIAGRAM
Revision Date: February 2000
Document No. 522 - 49 - 01
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com

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GS9000CCTJ equivalent
VDD
VDD
SWC
REXT
6k8
CEXT
EXTERNAL
COMPONENTS
Fig. 5 Pin 15 SWC
VDD
OUTPUT
GND
Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28
SWF, HSYNC, SSI, SSD, PCLK, PD0-9
SERIAL
CLOCK
(SCI)
tCLKL = tCLKH
50%
PARALLEL
DATA
(PDn)
1/2 T
1/2 T
SERIAL
DATA
(SDI)
PARALLEL
CLOCK
(PCLK)
50%
tSU tHOLD
Fig. 7 Waveforms
tD
TEST SET-UP & APPLICATION INFORMATION
Figure 8 shows the test set-up for the GS9000C operating
from a VDD supply of +5 volts. The differential pseudo ECL
inputs for DATA and CLOCK (pins 5,6,7 and 8) must be
biased between +3.0 and +4.0 volts. In the circuit shown,
these inputs with the resistor values shown, can be directly
driven from the outputs of the GS9005A Reclocking Receiver.
In other cases, such as true ECL level driver outputs, two
biasing resistors are needed on the DATA and CLOCK inputs
and the signals must be AC coupled.
It is critical that the decoupling capacitors connected to pins
12,13 and 18 be chip types and be located as close as
possible to the device pins.
In order to maintain very short interconnections when
interfacing with the GS9005A Receiver, the critical high
speed inputs such as Serial Data (pins 5 and 6) and Serial
Clock (pins 7 and 8) are located along one side of the device
package.
If the automatic standard select function is not used, the
Standard Select bits (pins 9 and 10) do not need to be
connected, however the control input (pin 11) should be
grounded.
5 522 - 49 - 01


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Featured Datasheets

Part NumberDescriptionMFRS
GS9000CCTJThe function is Serial Digital Decoder. ETCETC

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